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-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/atmega128rfa1.frt902
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/device.asm220
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/device.inc2808
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/device.py991
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/words/sleep.asm19
7 files changed, 0 insertions, 4988 deletions
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/atmega128rfa1.frt b/amforth-6.5/avr8/devices/atmega128rfa1/atmega128rfa1.frt
deleted file mode 100644
index 317ebd2..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/atmega128rfa1.frt
+++ /dev/null
@@ -1,902 +0,0 @@
-\ Partname: ATmega128RFA1
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART0 I/O Data Register
-&192 constant UCSR0A \ USART0 Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmit Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Frame Error
- $08 constant UCSR0A_DOR0 \ Data OverRun
- $04 constant UCSR0A_UPE0 \ USART Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART0 Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART0 Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART0 Baud Rate Register Bytes
-\ USART1
-&206 constant UDR1 \ USART1 I/O Data Register
-&200 constant UCSR1A \ USART1 Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmit Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Frame Error
- $08 constant UCSR1A_DOR1 \ Data OverRun
- $04 constant UCSR1A_UPE1 \ USART Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART Transmission Speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART1 Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART1 Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART1 Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \ TWI Address Mask
- $01 constant TWAMR_Res \ Reserved Bit
-&184 constant TWBR \ TWI Bit Rate Register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI START Condition Bit
- $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collision Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $02 constant TWCR_Res \ Reserved Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $04 constant TWSR_Res \ Reserved Bit
- $03 constant TWSR_TWPS \ TWI Prescaler Bits
-&187 constant TWDR \ TWI Data Register
-&186 constant TWAR \ TWI (Slave) Address Register
- $FE constant TWAR_TWA \ TWI (Slave) Address
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $3E constant SPSR_Res \ Reserved
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins Address
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins Address
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins Address
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins Address
-\ PORTE
-&46 constant PORTE \ Port E Data Register
-&45 constant DDRE \ Port E Data Direction Register
-&44 constant PINE \ Port E Input Pins Address
-\ PORTF
-&49 constant PORTF \ Port F Data Register
-&48 constant DDRF \ Port F Data Direction Register
-&47 constant PINF \ Port F Input Pins Address
-\ PORTG
-&52 constant PORTG \ Port G Data Register
-&51 constant DDRG \ Port G Data Direction Register
-&50 constant PING \ Port G Input Pins Address
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register B
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0 Register
-&69 constant TCCR0B \ Timer/Counter0 Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $30 constant TCCR0B_Res \ Reserved Bit
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter0 Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Match Output A Mode
- $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
- $0C constant TCCR0A_Res \ Reserved Bit
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $F8 constant TIMSK0_Res \ Reserved
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag Register
- $F8 constant TIFR0_Res \ Reserved
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare B Match Flag
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare A Match Flag
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $7C constant GTCCR_Res \ Reserved
- $02 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronous Timer/Counters
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $F8 constant TIMSK2_Res \ Reserved Bit
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $F8 constant TIFR2_Res \ Reserved Bit
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2 B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2 A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Match Output A Mode
- $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
- $0C constant TCCR2A_Res \ Reserved
- $03 constant TCCR2A_WGM2 \ Waveform Generation Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $30 constant TCCR2B_Res \ Reserved
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $80 constant ASSR_EXCLKAMR \ Enable External Clock Input for AMR
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mode
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare Register A Update Busy
- $04 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare Register B Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter2 Control Register A Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter2 Control Register B Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ TIMER_COUNTER_5
-&288 constant TCCR5A \ Timer/Counter5 Control Register A
- $C0 constant TCCR5A_COM5A \ Compare Output Mode for Channel A
- $30 constant TCCR5A_COM5B \ Compare Output Mode for Channel B
- $0C constant TCCR5A_COM5C \ Compare Output Mode for Channel C
- $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
-&289 constant TCCR5B \ Timer/Counter5 Control Register B
- $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceller
- $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
- $20 constant TCCR5B_Res \ Reserved Bit
- $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
- $07 constant TCCR5B_CS5 \ Clock Select
-&290 constant TCCR5C \ Timer/Counter5 Control Register C
- $80 constant TCCR5C_FOC5A \ Force Output Compare for Channel A
- $40 constant TCCR5C_FOC5B \ Force Output Compare for Channel B
- $20 constant TCCR5C_FOC5C \ Force Output Compare for Channel C
- $1F constant TCCR5C_Res \ Reserved
-&292 constant TCNT5 \ Timer/Counter5 Bytes
-&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
-&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
-&300 constant OCR5C \ Timer/Counter5 Output Compare Register C Bytes
-&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
-&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
- $C0 constant TIMSK5_Res \ Reserved Bit
- $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
- $10 constant TIMSK5_Res \ Reserved Bit
- $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
- $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
- $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
- $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
-&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag Register
- $C0 constant TIFR5_Res \ Reserved Bit
- $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture Flag
- $10 constant TIFR5_Res \ Reserved Bit
- $08 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare C Match Flag
- $04 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare B Match Flag
- $02 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare A Match Flag
- $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
-\ TIMER_COUNTER_4
-&160 constant TCCR4A \ Timer/Counter4 Control Register A
- $C0 constant TCCR4A_COM4A \ Compare Output Mode for Channel A
- $30 constant TCCR4A_COM4B \ Compare Output Mode for Channel B
- $0C constant TCCR4A_COM4C \ Compare Output Mode for Channel C
- $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
-&161 constant TCCR4B \ Timer/Counter4 Control Register B
- $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceller
- $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
- $20 constant TCCR4B_Res \ Reserved Bit
- $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
- $07 constant TCCR4B_CS4 \ Clock Select
-&162 constant TCCR4C \ Timer/Counter4 Control Register C
- $80 constant TCCR4C_FOC4A \ Force Output Compare for Channel A
- $40 constant TCCR4C_FOC4B \ Force Output Compare for Channel B
- $20 constant TCCR4C_FOC4C \ Force Output Compare for Channel C
- $1F constant TCCR4C_Res \ Reserved
-&164 constant TCNT4 \ Timer/Counter4 Bytes
-&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
-&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
-&172 constant OCR4C \ Timer/Counter4 Output Compare Register C Bytes
-&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
-&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
- $C0 constant TIMSK4_Res \ Reserved Bit
- $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
- $10 constant TIMSK4_Res \ Reserved Bit
- $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
- $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
- $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
- $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
-&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag Register
- $C0 constant TIFR4_Res \ Reserved Bit
- $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture Flag
- $10 constant TIFR4_Res \ Reserved Bit
- $08 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare C Match Flag
- $04 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare B Match Flag
- $02 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare A Match Flag
- $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
-\ TIMER_COUNTER_3
-&144 constant TCCR3A \ Timer/Counter3 Control Register A
- $C0 constant TCCR3A_COM3A \ Compare Output Mode for Channel A
- $30 constant TCCR3A_COM3B \ Compare Output Mode for Channel B
- $0C constant TCCR3A_COM3C \ Compare Output Mode for Channel C
- $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
-&145 constant TCCR3B \ Timer/Counter3 Control Register B
- $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceller
- $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
- $20 constant TCCR3B_Res \ Reserved Bit
- $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
- $07 constant TCCR3B_CS3 \ Clock Select
-&146 constant TCCR3C \ Timer/Counter3 Control Register C
- $80 constant TCCR3C_FOC3A \ Force Output Compare for Channel A
- $40 constant TCCR3C_FOC3B \ Force Output Compare for Channel B
- $20 constant TCCR3C_FOC3C \ Force Output Compare for Channel C
- $1F constant TCCR3C_Res \ Reserved
-&148 constant TCNT3 \ Timer/Counter3 Bytes
-&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
-&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
-&156 constant OCR3C \ Timer/Counter3 Output Compare Register C Bytes
-&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
-&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
- $C0 constant TIMSK3_Res \ Reserved Bit
- $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
- $10 constant TIMSK3_Res \ Reserved Bit
- $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
- $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
- $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
- $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
-&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag Register
- $C0 constant TIFR3_Res \ Reserved Bit
- $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture Flag
- $10 constant TIFR3_Res \ Reserved Bit
- $08 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare C Match Flag
- $04 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare B Match Flag
- $02 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare A Match Flag
- $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode for Channel A
- $30 constant TCCR1A_COM1B \ Compare Output Mode for Channel B
- $0C constant TCCR1A_COM1C \ Compare Output Mode for Channel C
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceller
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $20 constant TCCR1B_Res \ Reserved Bit
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Clock Select
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
- $20 constant TCCR1C_FOC1C \ Force Output Compare for Channel C
- $1F constant TCCR1C_Res \ Reserved
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $C0 constant TIMSK1_Res \ Reserved Bit
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $10 constant TIMSK1_Res \ Reserved Bit
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag Register
- $C0 constant TIFR1_Res \ Reserved Bit
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $10 constant TIFR1_Res \ Reserved Bit
- $08 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare C Match Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ TRX24
-&316 constant AES_CTRL \ AES Control Register
- $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
- $40 constant AES_CTRL_Res \ Reserved Bit
- $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
- $10 constant AES_CTRL_Res \ Reserved Bit
- $08 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
- $04 constant AES_CTRL_AES_IM \ AES Interrupt Enable
- $03 constant AES_CTRL_Res \ Reserved Bit
-&317 constant AES_STATUS \ AES Status Register
- $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Error
- $7E constant AES_STATUS_Res \ Reserved
- $01 constant AES_STATUS_AES_DONE \ AES Operation Finished with Success
-&318 constant AES_STATE \ AES Plain and Cipher Text Buffer Register
- $FF constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buffer
-&319 constant AES_KEY \ AES Encryption and Decryption Key Buffer Register
- $FF constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key Buffer
-&321 constant TRX_STATUS \ Transceiver Status Register
- $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
- $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
- $20 constant TRX_STATUS_TST_STATUS \ Test mode status
- $1F constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
-&322 constant TRX_STATE \ Transceiver State Control Register
- $E0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
- $1F constant TRX_STATE_TRX_CMD \ State Control Command
-&323 constant TRX_CTRL_0 \ Reserved
- $FF constant TRX_CTRL_0_Res \ Reserved
-&324 constant TRX_CTRL_1 \ Transceiver Control Register 1
- $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
- $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
- $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculation
- $1F constant TRX_CTRL_1_Res \ Reserved
-&325 constant PHY_TX_PWR \ Transceiver Transmit Power Control Register
- $C0 constant PHY_TX_PWR_PA_BUF_LT \ Power Amplifier Buffer Lead Time
- $30 constant PHY_TX_PWR_PA_LT \ Power Amplifier Lead Time
- $0F constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
-&326 constant PHY_RSSI \ Receiver Signal Strength Indicator Register
- $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
- $60 constant PHY_RSSI_RND_VALUE \ Random Value
- $1F constant PHY_RSSI_RSSI \ Receiver Signal Strength Indicator
-&327 constant PHY_ED_LEVEL \ Transceiver Energy Detection Level Register
- $FF constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
-&328 constant PHY_CC_CCA \ Transceiver Clear Channel Assessment (CCA) Control Register
- $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
- $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
- $1F constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
-&329 constant CCA_THRES \ Transceiver CCA Threshold Setting Register
- $F0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Measurement
- $0F constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Measurement
-&330 constant RX_CTRL \ Transceiver Receive Control Register
- $0F constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
-&331 constant SFD_VALUE \ Start of Frame Delimiter Value Register
- $FF constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
-&332 constant TRX_CTRL_2 \ Transceiver Control Register 2
- $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
- $7C constant TRX_CTRL_2_Res \ Reserved
- $03 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
-&333 constant ANT_DIV \ Antenna Diversity Control Register
- $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Status
- $70 constant ANT_DIV_Res \ Reserved
- $08 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
- $04 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch Control
- $03 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switch Control
-&334 constant IRQ_MASK \ Transceiver Interrupt Enable Register
- $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
- $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
- $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
- $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrupt Enable
- $08 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
- $04 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
- $02 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
- $01 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
-&335 constant IRQ_STATUS \ Transceiver Interrupt Status Register
- $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
- $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
- $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
- $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrupt Status
- $08 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
- $04 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
- $02 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
- $01 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
-&336 constant VREG_CTRL \ Voltage Regulator Control and Status Register
- $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
- $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
- $08 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
- $04 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
-&337 constant BATMON \ Battery Monitor Control and Status Register
- $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Status
- $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enable
- $20 constant BATMON_BATMON_OK \ Battery Monitor Status
- $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
- $0F constant BATMON_BATMON_VTH \ Battery Monitor Threshold Voltage
-&338 constant XOSC_CTRL \ Crystal Oscillator Control Register
- $F0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating Mode
- $0F constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capacitance Trimming
-&341 constant RX_SYN \ Transceiver Receiver Sensitivity Control Register
- $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
- $70 constant RX_SYN_Res \ Reserved
- $0F constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
-&343 constant XAH_CTRL_1 \ Transceiver Acknowledgment Frame Control Register 1
- $C0 constant XAH_CTRL_1_Res \ Reserved Bit
- $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
- $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
- $08 constant XAH_CTRL_1_Res \ Reserved Bit
- $04 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
- $02 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
- $01 constant XAH_CTRL_1_Res \ Reserved Bit
-&344 constant FTN_CTRL \ Transceiver Filter Tuning Control Register
- $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filter Tuning Network
-&346 constant PLL_CF \ Transceiver Center Frequency Calibration Control Register
- $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibration
-&347 constant PLL_DCU \ Transceiver Delay Cell Calibration Control Register
- $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
-&348 constant PART_NUM \ Device Identification Register (Part Number)
- $FF constant PART_NUM_PART_NUM \ Part Number
-&349 constant VERSION_NUM \ Device Identification Register (Version Number)
- $FF constant VERSION_NUM_VERSION_NUM \ Version Number
-&350 constant MAN_ID_0 \ Device Identification Register (Manufacture ID Low Byte)
- $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
- $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
- $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
- $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
- $08 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
- $04 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
- $02 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
- $01 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
-&351 constant MAN_ID_1 \ Device Identification Register (Manufacture ID High Byte)
- $FF constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
-&352 constant SHORT_ADDR_0 \ Transceiver MAC Short Address Register (Low Byte)
- $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
- $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
- $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
- $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
- $08 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
- $04 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
- $02 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
- $01 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
-&353 constant SHORT_ADDR_1 \ Transceiver MAC Short Address Register (High Byte)
- $FF constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
-&354 constant PAN_ID_0 \ Transceiver Personal Area Network ID Register (Low Byte)
- $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
- $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
- $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
- $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
- $08 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
- $04 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
- $02 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
- $01 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
-&355 constant PAN_ID_1 \ Transceiver Personal Area Network ID Register (High Byte)
- $FF constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
-&356 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address Register 0
- $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
- $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
- $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
- $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
- $08 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
- $04 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
- $02 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
- $01 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
-&357 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address Register 1
- $FF constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
-&358 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address Register 2
- $FF constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
-&359 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address Register 3
- $FF constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
-&360 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address Register 4
- $FF constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
-&361 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address Register 5
- $FF constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
-&362 constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address Register 6
- $FF constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
-&363 constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address Register 7
- $FF constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
-&364 constant XAH_CTRL_0 \ Transceiver Extended Operating Mode Control Register
- $F0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-transmission Attempts
- $0E constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Procedure Repetition Attempts
- $01 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
-&365 constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Number Generator Seed Register
- $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Number Generator
- $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Number Generator
- $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Number Generator
- $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Number Generator
- $08 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Number Generator
- $04 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Number Generator
- $02 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Number Generator
- $01 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Number Generator
-&366 constant CSMA_SEED_1 \ Transceiver Acknowledgment Frame Control Register 2
- $C0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mode
- $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
- $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame Transmission
- $08 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coordinator
- $07 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Number Generator
-&367 constant CSMA_BE \ Transceiver CSMA-CA Back-off Exponent Control Register
- $F0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
- $0F constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
-&374 constant TST_CTRL_DIGI \ Transceiver Digital Test Control Register
- $0F constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Register
-&379 constant TST_RX_LENGTH \ Transceiver Received Frame Length Register
- $FF constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
-&384 constant TRXFBST \ Start of frame buffer
-&511 constant TRXFBEND \ End of frame buffer
-\ SYMCNT
-&248 constant SCOCR1HH \ Symbol Counter Output Compare Register 1 HH-Byte
- $FF constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare Register 1 HH-Byte
-&247 constant SCOCR1HL \ Symbol Counter Output Compare Register 1 HL-Byte
- $FF constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare Register 1 HL-Byte
-&246 constant SCOCR1LH \ Symbol Counter Output Compare Register 1 LH-Byte
- $FF constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare Register 1 LH-Byte
-&245 constant SCOCR1LL \ Symbol Counter Output Compare Register 1 LL-Byte
- $FF constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare Register 1 LL-Byte
-&244 constant SCOCR2HH \ Symbol Counter Output Compare Register 2 HH-Byte
- $FF constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare Register 2 HH-Byte
-&243 constant SCOCR2HL \ Symbol Counter Output Compare Register 2 HL-Byte
- $FF constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare Register 2 HL-Byte
-&242 constant SCOCR2LH \ Symbol Counter Output Compare Register 2 LH-Byte
- $FF constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare Register 2 LH-Byte
-&241 constant SCOCR2LL \ Symbol Counter Output Compare Register 2 LL-Byte
- $FF constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare Register 2 LL-Byte
-&240 constant SCOCR3HH \ Symbol Counter Output Compare Register 3 HH-Byte
- $FF constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare Register 3 HH-Byte
-&239 constant SCOCR3HL \ Symbol Counter Output Compare Register 3 HL-Byte
- $FF constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare Register 3 HL-Byte
-&238 constant SCOCR3LH \ Symbol Counter Output Compare Register 3 LH-Byte
- $FF constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare Register 3 LH-Byte
-&237 constant SCOCR3LL \ Symbol Counter Output Compare Register 3 LL-Byte
- $FF constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare Register 3 LL-Byte
-&236 constant SCTSRHH \ Symbol Counter Frame Timestamp Register HH-Byte
- $FF constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp Register HH-Byte
-&235 constant SCTSRHL \ Symbol Counter Frame Timestamp Register HL-Byte
- $FF constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp Register HL-Byte
-&234 constant SCTSRLH \ Symbol Counter Frame Timestamp Register LH-Byte
- $FF constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp Register LH-Byte
-&233 constant SCTSRLL \ Symbol Counter Frame Timestamp Register LL-Byte
- $FF constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp Register LL-Byte
-&232 constant SCBTSRHH \ Symbol Counter Beacon Timestamp Register HH-Byte
- $FF constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestamp Register HH-Byte
-&231 constant SCBTSRHL \ Symbol Counter Beacon Timestamp Register HL-Byte
- $FF constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestamp Register HL-Byte
-&230 constant SCBTSRLH \ Symbol Counter Beacon Timestamp Register LH-Byte
- $FF constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestamp Register LH-Byte
-&229 constant SCBTSRLL \ Symbol Counter Beacon Timestamp Register LL-Byte
- $FF constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestamp Register LL-Byte
-&228 constant SCCNTHH \ Symbol Counter Register HH-Byte
- $FF constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byte
-&227 constant SCCNTHL \ Symbol Counter Register HL-Byte
- $FF constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byte
-&226 constant SCCNTLH \ Symbol Counter Register LH-Byte
- $FF constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byte
-&225 constant SCCNTLL \ Symbol Counter Register LL-Byte
- $FF constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byte
-&224 constant SCIRQS \ Symbol Counter Interrupt Status Register
- $E0 constant SCIRQS_Res \ Reserved Bit
- $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
- $08 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
- $07 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match IRQ
-&223 constant SCIRQM \ Symbol Counter Interrupt Mask Register
- $E0 constant SCIRQM_Res \ Reserved Bit
- $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enable
- $08 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ enable
- $07 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3 IRQ enable
-&222 constant SCSR \ Symbol Counter Status Register
- $FE constant SCSR_Res \ Reserved Bit
- $01 constant SCSR_SCBSY \ Symbol Counter busy
-&221 constant SCCR1 \ Symbol Counter Control Register 1
- $FE constant SCCR1_Res \ Reserved Bit
- $01 constant SCCR1_SCENBO \ Backoff Slot Counter enable
-&220 constant SCCR0 \ Symbol Counter Control Register 0
- $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
- $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
- $20 constant SCCR0_SCEN \ Symbol Counter enable
- $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source select
- $08 constant SCCR0_SCTSE \ Symbol Counter Automatic Timestamping enable
- $07 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3 Mode select
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $C0 constant EECR_Res \ Reserved
- $30 constant EECR_EEPM \ EEPROM Programming Mode
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Programming Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Register
- $FF constant OCDR_OCDR \ On-Chip Debug Register Data
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt 3 Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt 1 Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt 0 Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 5 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flag
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Mask
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Mask
-&107 constant PCMSK0 \ Pin Change Mask Register 0
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $F8 constant PCIFR_Res \ Reserved Bit
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $F8 constant PCICR_Res \ Reserved Bit
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC Multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status Register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&119 constant ADCSRC \ The ADC Control and Status Register C
- $C0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
- $20 constant ADCSRC_Res0 \ Reserved
- $1F constant ADCSRC_ADSUT \ ADC Start-up Time
-&125 constant DIDR2 \ Digital Input Disable Register 2
- $80 constant DIDR2_ADC15D \ Reserved Bits
- $40 constant DIDR2_ADC14D \ Reserved Bits
- $20 constant DIDR2_ADC13D \ Reserved Bits
- $10 constant DIDR2_ADC12D \ Reserved Bits
- $08 constant DIDR2_ADC11D \ Reserved Bits
- $04 constant DIDR2_ADC10D \ Reserved Bits
- $02 constant DIDR2_ADC9D \ Reserved Bits
- $01 constant DIDR2_ADC8D \ Reserved Bits
-&126 constant DIDR0 \ Digital Input Disable Register 0
- $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
- $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
- $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
- $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
- $08 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
- $04 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
- $02 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
- $01 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write Section Read Enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
- $FF constant OSCCAL_CAL \ Oscillator Calibration Tuning Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $70 constant CLKPR_Res \ Reserved
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&83 constant SMCR \ Sleep Mode Control Register
- $F0 constant SMCR_Res \ Reserved
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&91 constant RAMPZ \ Extended Z-pointer Register for ELPM/SPM
- $FC constant RAMPZ_Res \ Reserved
- $03 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value
-&75 constant GPIOR2 \ General Purpose I/O Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose I/O Register 2 Value
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose I/O Register 1 Value
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0 Value
- $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0 Value
- $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0 Value
- $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0 Value
- $08 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0 Value
- $04 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0 Value
- $02 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0 Value
- $01 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0 Value
-&99 constant PRR2 \ Power Reduction Register 2
- $F0 constant PRR2_Res \ Reserved Bit
- $0F constant PRR2_PRRAM \ Power Reduction SRAMs
-&101 constant PRR1 \ Power Reduction Register 1
- $80 constant PRR1_Res \ Reserved Bit
- $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
- $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
- $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
- $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
- $07 constant PRR1_PRUSART \ Reserved
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $10 constant PRR0_PRPGA \ Power Reduction PGA
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR0_PRUSART0 \ Power Reduction USART
- $01 constant PRR0_PRADC \ Power Reduction ADC
-\ FLASH
-&117 constant NEMCR \ Flash Extended-Mode Control-Register
- $40 constant NEMCR_ENEAM \ Enable Extended Address Mode for Extra Rows
- $30 constant NEMCR_AEAM \ Address for Extended Address Mode of Extra Rows
-&103 constant BGCR \ Reference Voltage Calibration Register
- $80 constant BGCR_Res \ Reserved Bit
- $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
- $07 constant BGCR_BGCAL \ Coarse Calibration Bits
-\ PWRCTRL
-&313 constant TRXPR \ Transceiver Pin Register
- $F0 constant TRXPR_Res \ Reserved
- $02 constant TRXPR_SLPTR \ Multi-purpose Transceiver Control Bit
- $01 constant TRXPR_TRXRST \ Force Transceiver Reset
-&309 constant DRTRAM0 \ Data Retention Configuration Register of SRAM 0
- $C0 constant DRTRAM0_Res \ Reserved
- $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
-&308 constant DRTRAM1 \ Data Retention Configuration Register of SRAM 1
- $C0 constant DRTRAM1_Res \ Reserved
- $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
-&307 constant DRTRAM2 \ Data Retention Configuration Register of SRAM 2
- $40 constant DRTRAM2_Res \ Reserved Bit
- $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
-&306 constant DRTRAM3 \ Data Retention Configuration Register of SRAM 3
- $C0 constant DRTRAM3_Res \ Reserved
- $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
- $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
-&304 constant LLDRL \ Low Leakage Voltage Regulator Data Register (Low-Byte)
- $F0 constant LLDRL_Res \ Reserved
- $0F constant LLDRL_LLDRL \ Low-Byte Data Register Bits
-&305 constant LLDRH \ Low Leakage Voltage Regulator Data Register (High-Byte)
- $E0 constant LLDRH_Res \ Reserved
- $1F constant LLDRH_LLDRH \ High-Byte Data Register Bits
-&303 constant LLCR \ Low Leakage Voltage Regulator Control Register
- $C0 constant LLCR_Res \ Reserved Bit
- $20 constant LLCR_LLDONE \ Calibration Done
- $10 constant LLCR_LLCOMP \ Comparator Output
- $08 constant LLCR_LLCAL \ Calibration Active
- $04 constant LLCR_LLTCO \ Temperature Coefficient of Current Source
- $02 constant LLCR_LLSHORT \ Short Lower Calibration Circuit
- $01 constant LLCR_LLENCAL \ Enable Automatic Calibration
-&310 constant DPDS0 \ Port Driver Strength Register 0
- $C0 constant DPDS0_PFDRV \ Driver Strength Port F
- $30 constant DPDS0_PEDRV \ Driver Strength Port E
- $0C constant DPDS0_PDDRV \ Driver Strength Port D
- $03 constant DPDS0_PBDRV \ Driver Strength Port B
-&311 constant DPDS1 \ Port Driver Strength Register 1
- $FC constant DPDS1_Res \ Reserved
- $03 constant DPDS1_PGDRV \ Driver Strength Port G
-\ USART0_SPI
-\ USART1_SPI
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&24 constant WDTAddr \ Watchdog Time-out Interrupt
-&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
-&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&48 constant SPI_STCAddr \ SPI Serial Transfer Complete
-&50 constant USART0_RXAddr \ USART0, Rx Complete
-&52 constant USART0_UDREAddr \ USART0 Data register Empty
-&54 constant USART0_TXAddr \ USART0, Tx Complete
-&56 constant ANALOG_COMPAddr \ Analog Comparator
-&58 constant ADCAddr \ ADC Conversion Complete
-&60 constant EE_READYAddr \ EEPROM Ready
-&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
-&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
-&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
-&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
-&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
-&72 constant USART1_RXAddr \ USART1, Rx Complete
-&74 constant USART1_UDREAddr \ USART1 Data register Empty
-&76 constant USART1_TXAddr \ USART1, Tx Complete
-&78 constant TWIAddr \ 2-wire Serial Interface
-&80 constant SPM_READYAddr \ Store Program Memory Read
-&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
-&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
-&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
-&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
-&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
-&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
-&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
-&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
-&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
-&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
-&102 constant USART2_RXAddr \ USART2, Rx Complete
-&104 constant USART2_UDREAddr \ USART2 Data register Empty
-&106 constant USART2_TXAddr \ USART2, Tx Complete
-&108 constant USART3_RXAddr \ USART3, Rx Complete
-&110 constant USART3_UDREAddr \ USART3 Data register Empty
-&112 constant USART3_TXAddr \ USART3, Tx Complete
-&114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt
-&116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt
-&118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt
-&120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt
-&122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt
-&124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI
-&126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt
-&128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state
-&130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt
-&132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt
-&134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt
-&136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt
-&138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt
-&140 constant AES_READYAddr \ AES engine ready interrupt
-&142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/device.asm b/amforth-6.5/avr8/devices/atmega128rfa1/device.asm
deleted file mode 100644
index e81539e..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/device.asm
+++ /dev/null
@@ -1,220 +0,0 @@
-; Partname: ATmega128RFA1
-; generated automatically, do not edit
-
-.nolist
- .include "m128RFA1def.inc"
-.list
-
-.equ ramstart = 512
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_USART1 = 0
-.set WANT_TWI = 0
-.set WANT_SPI = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_PORTG = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_TIMER_COUNTER_5 = 0
-.set WANT_TIMER_COUNTER_4 = 0
-.set WANT_TIMER_COUNTER_3 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TRX24 = 0
-.set WANT_SYMCNT = 0
-.set WANT_EEPROM = 0
-.set WANT_JTAG = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_CPU = 0
-.set WANT_FLASH = 0
-.set WANT_PWRCTRL = 0
-.set WANT_USART0_SPI = 0
-.set WANT_USART1_SPI = 0
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; Pin Change Interrupt Request 2
-.org 24
- rcall isr ; Watchdog Time-out Interrupt
-.org 26
- rcall isr ; Timer/Counter2 Compare Match A
-.org 28
- rcall isr ; Timer/Counter2 Compare Match B
-.org 30
- rcall isr ; Timer/Counter2 Overflow
-.org 32
- rcall isr ; Timer/Counter1 Capture Event
-.org 34
- rcall isr ; Timer/Counter1 Compare Match A
-.org 36
- rcall isr ; Timer/Counter1 Compare Match B
-.org 38
- rcall isr ; Timer/Counter1 Compare Match C
-.org 40
- rcall isr ; Timer/Counter1 Overflow
-.org 42
- rcall isr ; Timer/Counter0 Compare Match A
-.org 44
- rcall isr ; Timer/Counter0 Compare Match B
-.org 46
- rcall isr ; Timer/Counter0 Overflow
-.org 48
- rcall isr ; SPI Serial Transfer Complete
-.org 50
- rcall isr ; USART0, Rx Complete
-.org 52
- rcall isr ; USART0 Data register Empty
-.org 54
- rcall isr ; USART0, Tx Complete
-.org 56
- rcall isr ; Analog Comparator
-.org 58
- rcall isr ; ADC Conversion Complete
-.org 60
- rcall isr ; EEPROM Ready
-.org 62
- rcall isr ; Timer/Counter3 Capture Event
-.org 64
- rcall isr ; Timer/Counter3 Compare Match A
-.org 66
- rcall isr ; Timer/Counter3 Compare Match B
-.org 68
- rcall isr ; Timer/Counter3 Compare Match C
-.org 70
- rcall isr ; Timer/Counter3 Overflow
-.org 72
- rcall isr ; USART1, Rx Complete
-.org 74
- rcall isr ; USART1 Data register Empty
-.org 76
- rcall isr ; USART1, Tx Complete
-.org 78
- rcall isr ; 2-wire Serial Interface
-.org 80
- rcall isr ; Store Program Memory Read
-.org 82
- rcall isr ; Timer/Counter4 Capture Event
-.org 84
- rcall isr ; Timer/Counter4 Compare Match A
-.org 86
- rcall isr ; Timer/Counter4 Compare Match B
-.org 88
- rcall isr ; Timer/Counter4 Compare Match C
-.org 90
- rcall isr ; Timer/Counter4 Overflow
-.org 92
- rcall isr ; Timer/Counter5 Capture Event
-.org 94
- rcall isr ; Timer/Counter5 Compare Match A
-.org 96
- rcall isr ; Timer/Counter5 Compare Match B
-.org 98
- rcall isr ; Timer/Counter5 Compare Match C
-.org 100
- rcall isr ; Timer/Counter5 Overflow
-.org 102
- rcall isr ; USART2, Rx Complete
-.org 104
- rcall isr ; USART2 Data register Empty
-.org 106
- rcall isr ; USART2, Tx Complete
-.org 108
- rcall isr ; USART3, Rx Complete
-.org 110
- rcall isr ; USART3 Data register Empty
-.org 112
- rcall isr ; USART3, Tx Complete
-.org 114
- rcall isr ; TRX24 - PLL lock interrupt
-.org 116
- rcall isr ; TRX24 - PLL unlock interrupt
-.org 118
- rcall isr ; TRX24 - Receive start interrupt
-.org 120
- rcall isr ; TRX24 - RX_END interrupt
-.org 122
- rcall isr ; TRX24 - CCA/ED done interrupt
-.org 124
- rcall isr ; TRX24 - XAH - AMI
-.org 126
- rcall isr ; TRX24 - TX_END interrupt
-.org 128
- rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF
-.org 130
- rcall isr ; Symbol counter - compare match 1 interrupt
-.org 132
- rcall isr ; Symbol counter - compare match 2 interrupt
-.org 134
- rcall isr ; Symbol counter - compare match 3 interrupt
-.org 136
- rcall isr ; Symbol counter - overflow interrupt
-.org 138
- rcall isr ; Symbol counter - backoff interrupt
-.org 140
- rcall isr ; AES engine ready interrupt
-.org 142
- rcall isr ; Battery monitor indicates supply voltage below threshold
-.equ INTVECTORS = 72
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 16384
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 65535
-mcu_numints:
- .dw 72
-mcu_name:
- .dw 13
- .db "ATmega128RFA1",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/device.inc b/amforth-6.5/avr8/devices/atmega128rfa1/device.inc
deleted file mode 100644
index 503bb63..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/device.inc
+++ /dev/null
@@ -1,2808 +0,0 @@
-; Partname: ATmega128RFA1
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART0 I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART0 Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART0 Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART0 Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART0 Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART1 I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART1 Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART1 Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART1 Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART1 Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate Register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data Register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins Address
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins Address
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins Address
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins Address
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_PORTE == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Register
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Data Direction Register
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw 45
-; ( -- addr ) System Constant
-; R( -- )
-; Port E Input Pins Address
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw 44
-
-.endif
-.if WANT_PORTF == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port F Data Register
-VE_PORTF:
- .dw $ff05
- .db "PORTF",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTF
-XT_PORTF:
- .dw PFA_DOVARIABLE
-PFA_PORTF:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port F Data Direction Register
-VE_DDRF:
- .dw $ff04
- .db "DDRF"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRF
-XT_DDRF:
- .dw PFA_DOVARIABLE
-PFA_DDRF:
- .dw 48
-; ( -- addr ) System Constant
-; R( -- )
-; Port F Input Pins Address
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw 47
-
-.endif
-.if WANT_PORTG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Register
-VE_PORTG:
- .dw $ff05
- .db "PORTG",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTG
-XT_PORTG:
- .dw PFA_DOVARIABLE
-PFA_PORTG:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Data Direction Register
-VE_DDRG:
- .dw $ff04
- .db "DDRG"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRG
-XT_DDRG:
- .dw PFA_DOVARIABLE
-PFA_DDRG:
- .dw 51
-; ( -- addr ) System Constant
-; R( -- )
-; Port G Input Pins Address
-VE_PING:
- .dw $ff04
- .db "PING"
- .dw VE_HEAD
- .set VE_HEAD=VE_PING
-XT_PING:
- .dw PFA_DOVARIABLE
-PFA_PING:
- .dw 50
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register B
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag Register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_TIMER_COUNTER_5 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register A
-VE_TCCR5A:
- .dw $ff06
- .db "TCCR5A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5A
-XT_TCCR5A:
- .dw PFA_DOVARIABLE
-PFA_TCCR5A:
- .dw 288
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register B
-VE_TCCR5B:
- .dw $ff06
- .db "TCCR5B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5B
-XT_TCCR5B:
- .dw PFA_DOVARIABLE
-PFA_TCCR5B:
- .dw 289
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Control Register C
-VE_TCCR5C:
- .dw $ff06
- .db "TCCR5C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR5C
-XT_TCCR5C:
- .dw PFA_DOVARIABLE
-PFA_TCCR5C:
- .dw 290
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Bytes
-VE_TCNT5:
- .dw $ff05
- .db "TCNT5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT5
-XT_TCNT5:
- .dw PFA_DOVARIABLE
-PFA_TCNT5:
- .dw 292
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register A Bytes
-VE_OCR5A:
- .dw $ff05
- .db "OCR5A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5A
-XT_OCR5A:
- .dw PFA_DOVARIABLE
-PFA_OCR5A:
- .dw 296
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register B Bytes
-VE_OCR5B:
- .dw $ff05
- .db "OCR5B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5B
-XT_OCR5B:
- .dw PFA_DOVARIABLE
-PFA_OCR5B:
- .dw 298
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Output Compare Register C Bytes
-VE_OCR5C:
- .dw $ff05
- .db "OCR5C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR5C
-XT_OCR5C:
- .dw PFA_DOVARIABLE
-PFA_OCR5C:
- .dw 300
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Input Capture Register Bytes
-VE_ICR5:
- .dw $ff04
- .db "ICR5"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR5
-XT_ICR5:
- .dw PFA_DOVARIABLE
-PFA_ICR5:
- .dw 294
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Mask Register
-VE_TIMSK5:
- .dw $ff06
- .db "TIMSK5"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK5
-XT_TIMSK5:
- .dw PFA_DOVARIABLE
-PFA_TIMSK5:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter5 Interrupt Flag Register
-VE_TIFR5:
- .dw $ff05
- .db "TIFR5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR5
-XT_TIFR5:
- .dw PFA_DOVARIABLE
-PFA_TIFR5:
- .dw 58
-
-.endif
-.if WANT_TIMER_COUNTER_4 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register A
-VE_TCCR4A:
- .dw $ff06
- .db "TCCR4A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4A
-XT_TCCR4A:
- .dw PFA_DOVARIABLE
-PFA_TCCR4A:
- .dw 160
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register B
-VE_TCCR4B:
- .dw $ff06
- .db "TCCR4B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4B
-XT_TCCR4B:
- .dw PFA_DOVARIABLE
-PFA_TCCR4B:
- .dw 161
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Control Register C
-VE_TCCR4C:
- .dw $ff06
- .db "TCCR4C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR4C
-XT_TCCR4C:
- .dw PFA_DOVARIABLE
-PFA_TCCR4C:
- .dw 162
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Bytes
-VE_TCNT4:
- .dw $ff05
- .db "TCNT4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT4
-XT_TCNT4:
- .dw PFA_DOVARIABLE
-PFA_TCNT4:
- .dw 164
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register A Bytes
-VE_OCR4A:
- .dw $ff05
- .db "OCR4A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4A
-XT_OCR4A:
- .dw PFA_DOVARIABLE
-PFA_OCR4A:
- .dw 168
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register B Bytes
-VE_OCR4B:
- .dw $ff05
- .db "OCR4B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4B
-XT_OCR4B:
- .dw PFA_DOVARIABLE
-PFA_OCR4B:
- .dw 170
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Output Compare Register C Bytes
-VE_OCR4C:
- .dw $ff05
- .db "OCR4C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR4C
-XT_OCR4C:
- .dw PFA_DOVARIABLE
-PFA_OCR4C:
- .dw 172
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Input Capture Register Bytes
-VE_ICR4:
- .dw $ff04
- .db "ICR4"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR4
-XT_ICR4:
- .dw PFA_DOVARIABLE
-PFA_ICR4:
- .dw 166
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Mask Register
-VE_TIMSK4:
- .dw $ff06
- .db "TIMSK4"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK4
-XT_TIMSK4:
- .dw PFA_DOVARIABLE
-PFA_TIMSK4:
- .dw 114
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter4 Interrupt Flag Register
-VE_TIFR4:
- .dw $ff05
- .db "TIFR4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR4
-XT_TIFR4:
- .dw PFA_DOVARIABLE
-PFA_TIFR4:
- .dw 57
-
-.endif
-.if WANT_TIMER_COUNTER_3 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register A
-VE_TCCR3A:
- .dw $ff06
- .db "TCCR3A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3A
-XT_TCCR3A:
- .dw PFA_DOVARIABLE
-PFA_TCCR3A:
- .dw 144
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register B
-VE_TCCR3B:
- .dw $ff06
- .db "TCCR3B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3B
-XT_TCCR3B:
- .dw PFA_DOVARIABLE
-PFA_TCCR3B:
- .dw 145
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Control Register C
-VE_TCCR3C:
- .dw $ff06
- .db "TCCR3C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR3C
-XT_TCCR3C:
- .dw PFA_DOVARIABLE
-PFA_TCCR3C:
- .dw 146
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Bytes
-VE_TCNT3:
- .dw $ff05
- .db "TCNT3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT3
-XT_TCNT3:
- .dw PFA_DOVARIABLE
-PFA_TCNT3:
- .dw 148
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register A Bytes
-VE_OCR3A:
- .dw $ff05
- .db "OCR3A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3A
-XT_OCR3A:
- .dw PFA_DOVARIABLE
-PFA_OCR3A:
- .dw 152
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register B Bytes
-VE_OCR3B:
- .dw $ff05
- .db "OCR3B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3B
-XT_OCR3B:
- .dw PFA_DOVARIABLE
-PFA_OCR3B:
- .dw 154
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Output Compare Register C Bytes
-VE_OCR3C:
- .dw $ff05
- .db "OCR3C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR3C
-XT_OCR3C:
- .dw PFA_DOVARIABLE
-PFA_OCR3C:
- .dw 156
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Input Capture Register Bytes
-VE_ICR3:
- .dw $ff04
- .db "ICR3"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR3
-XT_ICR3:
- .dw PFA_DOVARIABLE
-PFA_ICR3:
- .dw 150
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Mask Register
-VE_TIMSK3:
- .dw $ff06
- .db "TIMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK3
-XT_TIMSK3:
- .dw PFA_DOVARIABLE
-PFA_TIMSK3:
- .dw 113
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter3 Interrupt Flag Register
-VE_TIFR3:
- .dw $ff05
- .db "TIFR3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR3
-XT_TIFR3:
- .dw PFA_DOVARIABLE
-PFA_TIFR3:
- .dw 56
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag Register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_TRX24 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; AES Control Register
-VE_AES_CTRL:
- .dw $ff08
- .db "AES_CTRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_AES_CTRL
-XT_AES_CTRL:
- .dw PFA_DOVARIABLE
-PFA_AES_CTRL:
- .dw 316
-; ( -- addr ) System Constant
-; R( -- )
-; AES Status Register
-VE_AES_STATUS:
- .dw $ff10
- .db "AES_STATUS"
- .dw VE_HEAD
- .set VE_HEAD=VE_AES_STATUS
-XT_AES_STATUS:
- .dw PFA_DOVARIABLE
-PFA_AES_STATUS:
- .dw 317
-; ( -- addr ) System Constant
-; R( -- )
-; AES Plain and Cipher Text Buffer Register
-VE_AES_STATE:
- .dw $ff09
- .db "AES_STATE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AES_STATE
-XT_AES_STATE:
- .dw PFA_DOVARIABLE
-PFA_AES_STATE:
- .dw 318
-; ( -- addr ) System Constant
-; R( -- )
-; AES Encryption and Decryption Key Buffer Register
-VE_AES_KEY:
- .dw $ff07
- .db "AES_KEY",0
- .dw VE_HEAD
- .set VE_HEAD=VE_AES_KEY
-XT_AES_KEY:
- .dw PFA_DOVARIABLE
-PFA_AES_KEY:
- .dw 319
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Status Register
-VE_TRX_STATUS:
- .dw $ff10
- .db "TRX_STATUS"
- .dw VE_HEAD
- .set VE_HEAD=VE_TRX_STATUS
-XT_TRX_STATUS:
- .dw PFA_DOVARIABLE
-PFA_TRX_STATUS:
- .dw 321
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver State Control Register
-VE_TRX_STATE:
- .dw $ff09
- .db "TRX_STATE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TRX_STATE
-XT_TRX_STATE:
- .dw PFA_DOVARIABLE
-PFA_TRX_STATE:
- .dw 322
-; ( -- addr ) System Constant
-; R( -- )
-; Reserved
-VE_TRX_CTRL_0:
- .dw $ff10
- .db "TRX_CTRL_0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TRX_CTRL_0
-XT_TRX_CTRL_0:
- .dw PFA_DOVARIABLE
-PFA_TRX_CTRL_0:
- .dw 323
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Control Register 1
-VE_TRX_CTRL_1:
- .dw $ff10
- .db "TRX_CTRL_1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TRX_CTRL_1
-XT_TRX_CTRL_1:
- .dw PFA_DOVARIABLE
-PFA_TRX_CTRL_1:
- .dw 324
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Transmit Power Control Register
-VE_PHY_TX_PWR:
- .dw $ff10
- .db "PHY_TX_PWR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PHY_TX_PWR
-XT_PHY_TX_PWR:
- .dw PFA_DOVARIABLE
-PFA_PHY_TX_PWR:
- .dw 325
-; ( -- addr ) System Constant
-; R( -- )
-; Receiver Signal Strength Indicator Register
-VE_PHY_RSSI:
- .dw $ff08
- .db "PHY_RSSI"
- .dw VE_HEAD
- .set VE_HEAD=VE_PHY_RSSI
-XT_PHY_RSSI:
- .dw PFA_DOVARIABLE
-PFA_PHY_RSSI:
- .dw 326
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Energy Detection Level Register
-VE_PHY_ED_LEVEL:
- .dw $ff12
- .db "PHY_ED_LEVEL"
- .dw VE_HEAD
- .set VE_HEAD=VE_PHY_ED_LEVEL
-XT_PHY_ED_LEVEL:
- .dw PFA_DOVARIABLE
-PFA_PHY_ED_LEVEL:
- .dw 327
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Clear Channel Assessment (CCA) Control Register
-VE_PHY_CC_CCA:
- .dw $ff10
- .db "PHY_CC_CCA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PHY_CC_CCA
-XT_PHY_CC_CCA:
- .dw PFA_DOVARIABLE
-PFA_PHY_CC_CCA:
- .dw 328
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver CCA Threshold Setting Register
-VE_CCA_THRES:
- .dw $ff09
- .db "CCA_THRES",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CCA_THRES
-XT_CCA_THRES:
- .dw PFA_DOVARIABLE
-PFA_CCA_THRES:
- .dw 329
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Receive Control Register
-VE_RX_CTRL:
- .dw $ff07
- .db "RX_CTRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RX_CTRL
-XT_RX_CTRL:
- .dw PFA_DOVARIABLE
-PFA_RX_CTRL:
- .dw 330
-; ( -- addr ) System Constant
-; R( -- )
-; Start of Frame Delimiter Value Register
-VE_SFD_VALUE:
- .dw $ff09
- .db "SFD_VALUE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFD_VALUE
-XT_SFD_VALUE:
- .dw PFA_DOVARIABLE
-PFA_SFD_VALUE:
- .dw 331
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Control Register 2
-VE_TRX_CTRL_2:
- .dw $ff10
- .db "TRX_CTRL_2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TRX_CTRL_2
-XT_TRX_CTRL_2:
- .dw PFA_DOVARIABLE
-PFA_TRX_CTRL_2:
- .dw 332
-; ( -- addr ) System Constant
-; R( -- )
-; Antenna Diversity Control Register
-VE_ANT_DIV:
- .dw $ff07
- .db "ANT_DIV",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ANT_DIV
-XT_ANT_DIV:
- .dw PFA_DOVARIABLE
-PFA_ANT_DIV:
- .dw 333
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Interrupt Enable Register
-VE_IRQ_MASK:
- .dw $ff08
- .db "IRQ_MASK"
- .dw VE_HEAD
- .set VE_HEAD=VE_IRQ_MASK
-XT_IRQ_MASK:
- .dw PFA_DOVARIABLE
-PFA_IRQ_MASK:
- .dw 334
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Interrupt Status Register
-VE_IRQ_STATUS:
- .dw $ff10
- .db "IRQ_STATUS"
- .dw VE_HEAD
- .set VE_HEAD=VE_IRQ_STATUS
-XT_IRQ_STATUS:
- .dw PFA_DOVARIABLE
-PFA_IRQ_STATUS:
- .dw 335
-; ( -- addr ) System Constant
-; R( -- )
-; Voltage Regulator Control and Status Register
-VE_VREG_CTRL:
- .dw $ff09
- .db "VREG_CTRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_VREG_CTRL
-XT_VREG_CTRL:
- .dw PFA_DOVARIABLE
-PFA_VREG_CTRL:
- .dw 336
-; ( -- addr ) System Constant
-; R( -- )
-; Battery Monitor Control and Status Register
-VE_BATMON:
- .dw $ff06
- .db "BATMON"
- .dw VE_HEAD
- .set VE_HEAD=VE_BATMON
-XT_BATMON:
- .dw PFA_DOVARIABLE
-PFA_BATMON:
- .dw 337
-; ( -- addr ) System Constant
-; R( -- )
-; Crystal Oscillator Control Register
-VE_XOSC_CTRL:
- .dw $ff09
- .db "XOSC_CTRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_XOSC_CTRL
-XT_XOSC_CTRL:
- .dw PFA_DOVARIABLE
-PFA_XOSC_CTRL:
- .dw 338
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Receiver Sensitivity Control Register
-VE_RX_SYN:
- .dw $ff06
- .db "RX_SYN"
- .dw VE_HEAD
- .set VE_HEAD=VE_RX_SYN
-XT_RX_SYN:
- .dw PFA_DOVARIABLE
-PFA_RX_SYN:
- .dw 341
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Acknowledgment Frame Control Register 1
-VE_XAH_CTRL_1:
- .dw $ff10
- .db "XAH_CTRL_1"
- .dw VE_HEAD
- .set VE_HEAD=VE_XAH_CTRL_1
-XT_XAH_CTRL_1:
- .dw PFA_DOVARIABLE
-PFA_XAH_CTRL_1:
- .dw 343
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Filter Tuning Control Register
-VE_FTN_CTRL:
- .dw $ff08
- .db "FTN_CTRL"
- .dw VE_HEAD
- .set VE_HEAD=VE_FTN_CTRL
-XT_FTN_CTRL:
- .dw PFA_DOVARIABLE
-PFA_FTN_CTRL:
- .dw 344
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Center Frequency Calibration Control Register
-VE_PLL_CF:
- .dw $ff06
- .db "PLL_CF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLL_CF
-XT_PLL_CF:
- .dw PFA_DOVARIABLE
-PFA_PLL_CF:
- .dw 346
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Delay Cell Calibration Control Register
-VE_PLL_DCU:
- .dw $ff07
- .db "PLL_DCU",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PLL_DCU
-XT_PLL_DCU:
- .dw PFA_DOVARIABLE
-PFA_PLL_DCU:
- .dw 347
-; ( -- addr ) System Constant
-; R( -- )
-; Device Identification Register (Part Number)
-VE_PART_NUM:
- .dw $ff08
- .db "PART_NUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_PART_NUM
-XT_PART_NUM:
- .dw PFA_DOVARIABLE
-PFA_PART_NUM:
- .dw 348
-; ( -- addr ) System Constant
-; R( -- )
-; Device Identification Register (Version Number)
-VE_VERSION_NUM:
- .dw $ff11
- .db "VERSION_NUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_VERSION_NUM
-XT_VERSION_NUM:
- .dw PFA_DOVARIABLE
-PFA_VERSION_NUM:
- .dw 349
-; ( -- addr ) System Constant
-; R( -- )
-; Device Identification Register (Manufacture ID Low Byte)
-VE_MAN_ID_0:
- .dw $ff08
- .db "MAN_ID_0"
- .dw VE_HEAD
- .set VE_HEAD=VE_MAN_ID_0
-XT_MAN_ID_0:
- .dw PFA_DOVARIABLE
-PFA_MAN_ID_0:
- .dw 350
-; ( -- addr ) System Constant
-; R( -- )
-; Device Identification Register (Manufacture ID High Byte)
-VE_MAN_ID_1:
- .dw $ff08
- .db "MAN_ID_1"
- .dw VE_HEAD
- .set VE_HEAD=VE_MAN_ID_1
-XT_MAN_ID_1:
- .dw PFA_DOVARIABLE
-PFA_MAN_ID_1:
- .dw 351
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC Short Address Register (Low Byte)
-VE_SHORT_ADDR_0:
- .dw $ff12
- .db "SHORT_ADDR_0"
- .dw VE_HEAD
- .set VE_HEAD=VE_SHORT_ADDR_0
-XT_SHORT_ADDR_0:
- .dw PFA_DOVARIABLE
-PFA_SHORT_ADDR_0:
- .dw 352
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC Short Address Register (High Byte)
-VE_SHORT_ADDR_1:
- .dw $ff12
- .db "SHORT_ADDR_1"
- .dw VE_HEAD
- .set VE_HEAD=VE_SHORT_ADDR_1
-XT_SHORT_ADDR_1:
- .dw PFA_DOVARIABLE
-PFA_SHORT_ADDR_1:
- .dw 353
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Personal Area Network ID Register (Low Byte)
-VE_PAN_ID_0:
- .dw $ff08
- .db "PAN_ID_0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PAN_ID_0
-XT_PAN_ID_0:
- .dw PFA_DOVARIABLE
-PFA_PAN_ID_0:
- .dw 354
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Personal Area Network ID Register (High Byte)
-VE_PAN_ID_1:
- .dw $ff08
- .db "PAN_ID_1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PAN_ID_1
-XT_PAN_ID_1:
- .dw PFA_DOVARIABLE
-PFA_PAN_ID_1:
- .dw 355
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 0
-VE_IEEE_ADDR_0:
- .dw $ff11
- .db "IEEE_ADDR_0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_0
-XT_IEEE_ADDR_0:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_0:
- .dw 356
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 1
-VE_IEEE_ADDR_1:
- .dw $ff11
- .db "IEEE_ADDR_1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_1
-XT_IEEE_ADDR_1:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_1:
- .dw 357
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 2
-VE_IEEE_ADDR_2:
- .dw $ff11
- .db "IEEE_ADDR_2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_2
-XT_IEEE_ADDR_2:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_2:
- .dw 358
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 3
-VE_IEEE_ADDR_3:
- .dw $ff11
- .db "IEEE_ADDR_3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_3
-XT_IEEE_ADDR_3:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_3:
- .dw 359
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 4
-VE_IEEE_ADDR_4:
- .dw $ff11
- .db "IEEE_ADDR_4",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_4
-XT_IEEE_ADDR_4:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_4:
- .dw 360
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 5
-VE_IEEE_ADDR_5:
- .dw $ff11
- .db "IEEE_ADDR_5",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_5
-XT_IEEE_ADDR_5:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_5:
- .dw 361
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 6
-VE_IEEE_ADDR_6:
- .dw $ff11
- .db "IEEE_ADDR_6",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_6
-XT_IEEE_ADDR_6:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_6:
- .dw 362
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver MAC IEEE Address Register 7
-VE_IEEE_ADDR_7:
- .dw $ff11
- .db "IEEE_ADDR_7",0
- .dw VE_HEAD
- .set VE_HEAD=VE_IEEE_ADDR_7
-XT_IEEE_ADDR_7:
- .dw PFA_DOVARIABLE
-PFA_IEEE_ADDR_7:
- .dw 363
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Extended Operating Mode Control Register
-VE_XAH_CTRL_0:
- .dw $ff10
- .db "XAH_CTRL_0"
- .dw VE_HEAD
- .set VE_HEAD=VE_XAH_CTRL_0
-XT_XAH_CTRL_0:
- .dw PFA_DOVARIABLE
-PFA_XAH_CTRL_0:
- .dw 364
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver CSMA-CA Random Number Generator Seed Register
-VE_CSMA_SEED_0:
- .dw $ff11
- .db "CSMA_SEED_0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CSMA_SEED_0
-XT_CSMA_SEED_0:
- .dw PFA_DOVARIABLE
-PFA_CSMA_SEED_0:
- .dw 365
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Acknowledgment Frame Control Register 2
-VE_CSMA_SEED_1:
- .dw $ff11
- .db "CSMA_SEED_1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CSMA_SEED_1
-XT_CSMA_SEED_1:
- .dw PFA_DOVARIABLE
-PFA_CSMA_SEED_1:
- .dw 366
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver CSMA-CA Back-off Exponent Control Register
-VE_CSMA_BE:
- .dw $ff07
- .db "CSMA_BE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CSMA_BE
-XT_CSMA_BE:
- .dw PFA_DOVARIABLE
-PFA_CSMA_BE:
- .dw 367
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Digital Test Control Register
-VE_TST_CTRL_DIGI:
- .dw $ff13
- .db "TST_CTRL_DIGI",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TST_CTRL_DIGI
-XT_TST_CTRL_DIGI:
- .dw PFA_DOVARIABLE
-PFA_TST_CTRL_DIGI:
- .dw 374
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Received Frame Length Register
-VE_TST_RX_LENGTH:
- .dw $ff13
- .db "TST_RX_LENGTH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TST_RX_LENGTH
-XT_TST_RX_LENGTH:
- .dw PFA_DOVARIABLE
-PFA_TST_RX_LENGTH:
- .dw 379
-; ( -- addr ) System Constant
-; R( -- )
-; Start of frame buffer
-VE_TRXFBST:
- .dw $ff07
- .db "TRXFBST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TRXFBST
-XT_TRXFBST:
- .dw PFA_DOVARIABLE
-PFA_TRXFBST:
- .dw 384
-; ( -- addr ) System Constant
-; R( -- )
-; End of frame buffer
-VE_TRXFBEND:
- .dw $ff08
- .db "TRXFBEND"
- .dw VE_HEAD
- .set VE_HEAD=VE_TRXFBEND
-XT_TRXFBEND:
- .dw PFA_DOVARIABLE
-PFA_TRXFBEND:
- .dw 511
-
-.endif
-.if WANT_SYMCNT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 1 HH-Byte
-VE_SCOCR1HH:
- .dw $ff08
- .db "SCOCR1HH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR1HH
-XT_SCOCR1HH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR1HH:
- .dw 248
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 1 HL-Byte
-VE_SCOCR1HL:
- .dw $ff08
- .db "SCOCR1HL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR1HL
-XT_SCOCR1HL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR1HL:
- .dw 247
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 1 LH-Byte
-VE_SCOCR1LH:
- .dw $ff08
- .db "SCOCR1LH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR1LH
-XT_SCOCR1LH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR1LH:
- .dw 246
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 1 LL-Byte
-VE_SCOCR1LL:
- .dw $ff08
- .db "SCOCR1LL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR1LL
-XT_SCOCR1LL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR1LL:
- .dw 245
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 2 HH-Byte
-VE_SCOCR2HH:
- .dw $ff08
- .db "SCOCR2HH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR2HH
-XT_SCOCR2HH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR2HH:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 2 HL-Byte
-VE_SCOCR2HL:
- .dw $ff08
- .db "SCOCR2HL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR2HL
-XT_SCOCR2HL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR2HL:
- .dw 243
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 2 LH-Byte
-VE_SCOCR2LH:
- .dw $ff08
- .db "SCOCR2LH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR2LH
-XT_SCOCR2LH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR2LH:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 2 LL-Byte
-VE_SCOCR2LL:
- .dw $ff08
- .db "SCOCR2LL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR2LL
-XT_SCOCR2LL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR2LL:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 3 HH-Byte
-VE_SCOCR3HH:
- .dw $ff08
- .db "SCOCR3HH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR3HH
-XT_SCOCR3HH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR3HH:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 3 HL-Byte
-VE_SCOCR3HL:
- .dw $ff08
- .db "SCOCR3HL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR3HL
-XT_SCOCR3HL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR3HL:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 3 LH-Byte
-VE_SCOCR3LH:
- .dw $ff08
- .db "SCOCR3LH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR3LH
-XT_SCOCR3LH:
- .dw PFA_DOVARIABLE
-PFA_SCOCR3LH:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Output Compare Register 3 LL-Byte
-VE_SCOCR3LL:
- .dw $ff08
- .db "SCOCR3LL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCOCR3LL
-XT_SCOCR3LL:
- .dw PFA_DOVARIABLE
-PFA_SCOCR3LL:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Frame Timestamp Register HH-Byte
-VE_SCTSRHH:
- .dw $ff07
- .db "SCTSRHH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCTSRHH
-XT_SCTSRHH:
- .dw PFA_DOVARIABLE
-PFA_SCTSRHH:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Frame Timestamp Register HL-Byte
-VE_SCTSRHL:
- .dw $ff07
- .db "SCTSRHL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCTSRHL
-XT_SCTSRHL:
- .dw PFA_DOVARIABLE
-PFA_SCTSRHL:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Frame Timestamp Register LH-Byte
-VE_SCTSRLH:
- .dw $ff07
- .db "SCTSRLH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCTSRLH
-XT_SCTSRLH:
- .dw PFA_DOVARIABLE
-PFA_SCTSRLH:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Frame Timestamp Register LL-Byte
-VE_SCTSRLL:
- .dw $ff07
- .db "SCTSRLL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCTSRLL
-XT_SCTSRLL:
- .dw PFA_DOVARIABLE
-PFA_SCTSRLL:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Beacon Timestamp Register HH-Byte
-VE_SCBTSRHH:
- .dw $ff08
- .db "SCBTSRHH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCBTSRHH
-XT_SCBTSRHH:
- .dw PFA_DOVARIABLE
-PFA_SCBTSRHH:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Beacon Timestamp Register HL-Byte
-VE_SCBTSRHL:
- .dw $ff08
- .db "SCBTSRHL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCBTSRHL
-XT_SCBTSRHL:
- .dw PFA_DOVARIABLE
-PFA_SCBTSRHL:
- .dw 231
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Beacon Timestamp Register LH-Byte
-VE_SCBTSRLH:
- .dw $ff08
- .db "SCBTSRLH"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCBTSRLH
-XT_SCBTSRLH:
- .dw PFA_DOVARIABLE
-PFA_SCBTSRLH:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Beacon Timestamp Register LL-Byte
-VE_SCBTSRLL:
- .dw $ff08
- .db "SCBTSRLL"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCBTSRLL
-XT_SCBTSRLL:
- .dw PFA_DOVARIABLE
-PFA_SCBTSRLL:
- .dw 229
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Register HH-Byte
-VE_SCCNTHH:
- .dw $ff07
- .db "SCCNTHH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCNTHH
-XT_SCCNTHH:
- .dw PFA_DOVARIABLE
-PFA_SCCNTHH:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Register HL-Byte
-VE_SCCNTHL:
- .dw $ff07
- .db "SCCNTHL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCNTHL
-XT_SCCNTHL:
- .dw PFA_DOVARIABLE
-PFA_SCCNTHL:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Register LH-Byte
-VE_SCCNTLH:
- .dw $ff07
- .db "SCCNTLH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCNTLH
-XT_SCCNTLH:
- .dw PFA_DOVARIABLE
-PFA_SCCNTLH:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Register LL-Byte
-VE_SCCNTLL:
- .dw $ff07
- .db "SCCNTLL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCNTLL
-XT_SCCNTLL:
- .dw PFA_DOVARIABLE
-PFA_SCCNTLL:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Interrupt Status Register
-VE_SCIRQS:
- .dw $ff06
- .db "SCIRQS"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCIRQS
-XT_SCIRQS:
- .dw PFA_DOVARIABLE
-PFA_SCIRQS:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Interrupt Mask Register
-VE_SCIRQM:
- .dw $ff06
- .db "SCIRQM"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCIRQM
-XT_SCIRQM:
- .dw PFA_DOVARIABLE
-PFA_SCIRQM:
- .dw 223
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Status Register
-VE_SCSR:
- .dw $ff04
- .db "SCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SCSR
-XT_SCSR:
- .dw PFA_DOVARIABLE
-PFA_SCSR:
- .dw 222
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Control Register 1
-VE_SCCR1:
- .dw $ff05
- .db "SCCR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCR1
-XT_SCCR1:
- .dw PFA_DOVARIABLE
-PFA_SCCR1:
- .dw 221
-; ( -- addr ) System Constant
-; R( -- )
-; Symbol Counter Control Register 0
-VE_SCCR0:
- .dw $ff05
- .db "SCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SCCR0
-XT_SCCR0:
- .dw PFA_DOVARIABLE
-PFA_SCCR0:
- .dw 220
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Register
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status Register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status Register C
-VE_ADCSRC:
- .dw $ff06
- .db "ADCSRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRC
-XT_ADCSRC:
- .dw PFA_DOVARIABLE
-PFA_ADCSRC:
- .dw 119
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 2
-VE_DIDR2:
- .dw $ff05
- .db "DIDR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR2
-XT_DIDR2:
- .dw PFA_DOVARIABLE
-PFA_DIDR2:
- .dw 125
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 0
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Z-pointer Register for ELPM/SPM
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register 2
-VE_PRR2:
- .dw $ff04
- .db "PRR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR2
-XT_PRR2:
- .dw PFA_DOVARIABLE
-PFA_PRR2:
- .dw 99
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register 1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
-.if WANT_FLASH == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Flash Extended-Mode Control-Register
-VE_NEMCR:
- .dw $ff05
- .db "NEMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_NEMCR
-XT_NEMCR:
- .dw PFA_DOVARIABLE
-PFA_NEMCR:
- .dw 117
-; ( -- addr ) System Constant
-; R( -- )
-; Reference Voltage Calibration Register
-VE_BGCR:
- .dw $ff04
- .db "BGCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_BGCR
-XT_BGCR:
- .dw PFA_DOVARIABLE
-PFA_BGCR:
- .dw 103
-
-.endif
-.if WANT_PWRCTRL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Transceiver Pin Register
-VE_TRXPR:
- .dw $ff05
- .db "TRXPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TRXPR
-XT_TRXPR:
- .dw PFA_DOVARIABLE
-PFA_TRXPR:
- .dw 313
-; ( -- addr ) System Constant
-; R( -- )
-; Data Retention Configuration Register of SRAM 0
-VE_DRTRAM0:
- .dw $ff07
- .db "DRTRAM0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DRTRAM0
-XT_DRTRAM0:
- .dw PFA_DOVARIABLE
-PFA_DRTRAM0:
- .dw 309
-; ( -- addr ) System Constant
-; R( -- )
-; Data Retention Configuration Register of SRAM 1
-VE_DRTRAM1:
- .dw $ff07
- .db "DRTRAM1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DRTRAM1
-XT_DRTRAM1:
- .dw PFA_DOVARIABLE
-PFA_DRTRAM1:
- .dw 308
-; ( -- addr ) System Constant
-; R( -- )
-; Data Retention Configuration Register of SRAM 2
-VE_DRTRAM2:
- .dw $ff07
- .db "DRTRAM2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DRTRAM2
-XT_DRTRAM2:
- .dw PFA_DOVARIABLE
-PFA_DRTRAM2:
- .dw 307
-; ( -- addr ) System Constant
-; R( -- )
-; Data Retention Configuration Register of SRAM 3
-VE_DRTRAM3:
- .dw $ff07
- .db "DRTRAM3",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DRTRAM3
-XT_DRTRAM3:
- .dw PFA_DOVARIABLE
-PFA_DRTRAM3:
- .dw 306
-; ( -- addr ) System Constant
-; R( -- )
-; Low Leakage Voltage Regulator Data Register (Low-Byte)
-VE_LLDRL:
- .dw $ff05
- .db "LLDRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LLDRL
-XT_LLDRL:
- .dw PFA_DOVARIABLE
-PFA_LLDRL:
- .dw 304
-; ( -- addr ) System Constant
-; R( -- )
-; Low Leakage Voltage Regulator Data Register (High-Byte)
-VE_LLDRH:
- .dw $ff05
- .db "LLDRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_LLDRH
-XT_LLDRH:
- .dw PFA_DOVARIABLE
-PFA_LLDRH:
- .dw 305
-; ( -- addr ) System Constant
-; R( -- )
-; Low Leakage Voltage Regulator Control Register
-VE_LLCR:
- .dw $ff04
- .db "LLCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_LLCR
-XT_LLCR:
- .dw PFA_DOVARIABLE
-PFA_LLCR:
- .dw 303
-; ( -- addr ) System Constant
-; R( -- )
-; Port Driver Strength Register 0
-VE_DPDS0:
- .dw $ff05
- .db "DPDS0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DPDS0
-XT_DPDS0:
- .dw PFA_DOVARIABLE
-PFA_DPDS0:
- .dw 310
-; ( -- addr ) System Constant
-; R( -- )
-; Port Driver Strength Register 1
-VE_DPDS1:
- .dw $ff05
- .db "DPDS1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DPDS1
-XT_DPDS1:
- .dw PFA_DOVARIABLE
-PFA_DPDS1:
- .dw 311
-
-.endif
-.if WANT_USART0_SPI == 1
-
-.endif
-.if WANT_USART1_SPI == 1
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/device.py b/amforth-6.5/avr8/devices/atmega128rfa1/device.py
deleted file mode 100644
index 3e24dfa..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/device.py
+++ /dev/null
@@ -1,991 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega128RFA1
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'INT3Addr' : '#8', # External Interrupt Request 3
- 'INT4Addr' : '#10', # External Interrupt Request 4
- 'INT5Addr' : '#12', # External Interrupt Request 5
- 'INT6Addr' : '#14', # External Interrupt Request 6
- 'INT7Addr' : '#16', # External Interrupt Request 7
- 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
- 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
- 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
- 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#50', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
- 'USART0_TXAddr' : '#54', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#56', # Analog Comparator
- 'ADCAddr' : '#58', # ADC Conversion Complete
- 'EE_READYAddr' : '#60', # EEPROM Ready
- 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
- 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
- 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
- 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
- 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
- 'USART1_RXAddr' : '#72', # USART1, Rx Complete
- 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
- 'USART1_TXAddr' : '#76', # USART1, Tx Complete
- 'TWIAddr' : '#78', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#80', # Store Program Memory Read
- 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
- 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
- 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
- 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
- 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
- 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
- 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
- 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
- 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
- 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
- 'USART2_RXAddr' : '#102', # USART2, Rx Complete
- 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
- 'USART2_TXAddr' : '#106', # USART2, Tx Complete
- 'USART3_RXAddr' : '#108', # USART3, Rx Complete
- 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
- 'USART3_TXAddr' : '#112', # USART3, Tx Complete
- 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt
- 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt
- 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt
- 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt
- 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt
- 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI
- 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt
- 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF
- 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt
- 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt
- 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt
- 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt
- 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt
- 'AES_READYAddr' : '#140', # AES engine ready interrupt
- 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART0 I/O Data Register
- 'UCSR0A' : '$c0', # USART0 Control and Status Regi
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Frame Error
- 'UCSR0A_DOR0': '$8', # Data OverRun
- 'UCSR0A_UPE0': '$4', # USART Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART Transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART0 Control and Status Regi
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART0 Control and Status Regi
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt
-
-# Module USART1
- 'UDR1' : '$ce', # USART1 I/O Data Register
- 'UCSR1A' : '$c8', # USART1 Control and Status Regi
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Frame Error
- 'UCSR1A_DOR1': '$8', # Data OverRun
- 'UCSR1A_UPE1': '$4', # USART Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART Transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART1 Control and Status Regi
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART1 Control and Status Regi
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', # TWI Address Mask
- 'TWAMR_Res': '$1', # Reserved Bit
- 'TWBR' : '$b8', # TWI Bit Rate Register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI START Condition Bit
- 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collision Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_Res': '$2', # Reserved Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_Res': '$4', # Reserved Bit
- 'TWSR_TWPS': '$3', # TWI Prescaler Bits
- 'TWDR' : '$bb', # TWI Data Register
- 'TWAR' : '$ba', # TWI (Slave) Address Register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module SPI
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_Res': '$3e', # Reserved
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPDR' : '$4e', # SPI Data Register
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins Address
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins Address
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins Address
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins Address
-
-# Module PORTE
- 'PORTE' : '$2e', # Port E Data Register
- 'DDRE' : '$2d', # Port E Data Direction Register
- 'PINE' : '$2c', # Port E Input Pins Address
-
-# Module PORTF
- 'PORTF' : '$31', # Port F Data Register
- 'DDRF' : '$30', # Port F Data Direction Register
- 'PINF' : '$2f', # Port F Input Pins Address
-
-# Module PORTG
- 'PORTG' : '$34', # Port G Data Register
- 'DDRG' : '$33', # Port G Data Direction Register
- 'PING' : '$32', # Port G Input Pins Address
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0 Register
- 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_Res': '$30', # Reserved Bit
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode
- 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode
- 'TCCR0A_Res': '$c', # Reserved Bit
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_Res': '$f8', # Reserved
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_Res': '$f8', # Reserved
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_Res': '$7c', # Reserved
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_Res': '$f8', # Reserved Bit
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_Res': '$f8', # Reserved Bit
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode
- 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode
- 'TCCR2A_Res': '$c', # Reserved
- 'TCCR2A_WGM2': '$3', # Waveform Generation Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_Res': '$30', # Reserved
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare
- 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare
- 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe
- 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module TIMER_COUNTER_5
- 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
- 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe
- 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe
- 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe
- 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
- 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
- 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle
- 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
- 'TCCR5B_Res': '$20', # Reserved Bit
- 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
- 'TCCR5B_CS5': '$7', # Clock Select
- 'TCCR5C' : '$122', # Timer/Counter5 Control Registe
- 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann
- 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann
- 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann
- 'TCCR5C_Res': '$1f', # Reserved
- 'TCNT5' : '$124', # Timer/Counter5 Bytes
- 'OCR5A' : '$128', # Timer/Counter5 Output Compare
- 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
- 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
- 'ICR5' : '$126', # Timer/Counter5 Input Capture R
- 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
- 'TIMSK5_Res': '$c0', # Reserved Bit
- 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
- 'TIMSK5_Res': '$10', # Reserved Bit
- 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
- 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
- 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
- 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
- 'TIFR5_Res': '$c0', # Reserved Bit
- 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F
- 'TIFR5_Res': '$10', # Reserved Bit
- 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare
- 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare
- 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
-
-# Module TIMER_COUNTER_4
- 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
- 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe
- 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe
- 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe
- 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
- 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
- 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle
- 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
- 'TCCR4B_Res': '$20', # Reserved Bit
- 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
- 'TCCR4B_CS4': '$7', # Clock Select
- 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe
- 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann
- 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann
- 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann
- 'TCCR4C_Res': '$1f', # Reserved
- 'TCNT4' : '$a4', # Timer/Counter4 Bytes
- 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
- 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
- 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
- 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
- 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
- 'TIMSK4_Res': '$c0', # Reserved Bit
- 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
- 'TIMSK4_Res': '$10', # Reserved Bit
- 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
- 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
- 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
- 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
- 'TIFR4_Res': '$c0', # Reserved Bit
- 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F
- 'TIFR4_Res': '$10', # Reserved Bit
- 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare
- 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare
- 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
-
-# Module TIMER_COUNTER_3
- 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
- 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe
- 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe
- 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe
- 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
- 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
- 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle
- 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
- 'TCCR3B_Res': '$20', # Reserved Bit
- 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
- 'TCCR3B_CS3': '$7', # Clock Select
- 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
- 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
- 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
- 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann
- 'TCCR3C_Res': '$1f', # Reserved
- 'TCNT3' : '$94', # Timer/Counter3 Bytes
- 'OCR3A' : '$98', # Timer/Counter3 Output Compare
- 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
- 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
- 'ICR3' : '$96', # Timer/Counter3 Input Capture R
- 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
- 'TIMSK3_Res': '$c0', # Reserved Bit
- 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
- 'TIMSK3_Res': '$10', # Reserved Bit
- 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
- 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
- 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
- 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
- 'TIFR3_Res': '$c0', # Reserved Bit
- 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
- 'TIFR3_Res': '$10', # Reserved Bit
- 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
- 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
- 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
-
-# Module TIMER_COUNTER_1
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe
- 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe
- 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_Res': '$20', # Reserved Bit
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Clock Select
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann
- 'TCCR1C_Res': '$1f', # Reserved
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_Res': '$c0', # Reserved Bit
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_Res': '$10', # Reserved Bit
- 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
- 'TIFR1_Res': '$c0', # Reserved Bit
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_Res': '$10', # Reserved Bit
- 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
-
-# Module TRX24
- 'AES_CTRL' : '$13c', # AES Control Register
- 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation.
- 'AES_CTRL_Res': '$40', # Reserved Bit
- 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode
- 'AES_CTRL_Res': '$10', # Reserved Bit
- 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction
- 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable
- 'AES_CTRL_Res': '$3', # Reserved Bit
- 'AES_STATUS' : '$13d', # AES Status Register
- 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er
- 'AES_STATUS_Res': '$7e', # Reserved
- 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su
- 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff
- 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff
- 'AES_KEY' : '$13f', # AES Encryption and Decryption
- 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key
- 'TRX_STATUS' : '$141', # Transceiver Status Register
- 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status
- 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result
- 'TRX_STATUS_TST_STATUS': '$20', # Test mode status
- 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status
- 'TRX_STATE' : '$142', # Transceiver State Control Regi
- 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status
- 'TRX_STATE_TRX_CMD': '$1f', # State Control Command
- 'TRX_CTRL_0' : '$143', # Reserved
- 'TRX_CTRL_0_Res': '$ff', # Reserved
- 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1
- 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable
- 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1
- 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati
- 'TRX_CTRL_1_Res': '$1f', # Reserved
- 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con
- 'PHY_TX_PWR_PA_BUF_LT': '$c0', # Power Amplifier Buffer Lead Ti
- 'PHY_TX_PWR_PA_LT': '$30', # Power Amplifier Lead Time
- 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting
- 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic
- 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status
- 'PHY_RSSI_RND_VALUE': '$60', # Random Value
- 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic
- 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L
- 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level
- 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse
- 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request
- 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode
- 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection
- 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett
- 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea
- 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea
- 'RX_CTRL' : '$14a', # Transceiver Receive Control Re
- 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control
- 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value
- 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value
- 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2
- 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode
- 'TRX_CTRL_2_Res': '$7c', # Reserved
- 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection
- 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi
- 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat
- 'ANT_DIV_Res': '$70', # Reserved
- 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity
- 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch
- 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc
- 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R
- 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable
- 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable
- 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable
- 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup
- 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable
- 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable
- 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable
- 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable
- 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R
- 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status
- 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status
- 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status
- 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup
- 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status
- 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status
- 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status
- 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status
- 'VREG_CTRL' : '$150', # Voltage Regulator Control and
- 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator
- 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid
- 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator
- 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid
- 'BATMON' : '$151', # Battery Monitor Control and St
- 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat
- 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab
- 'BATMON_BATMON_OK': '$20', # Battery Monitor Status
- 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range
- 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt
- 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg
- 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M
- 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci
- 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi
- 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception
- 'RX_SYN_Res': '$70', # Reserved
- 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity
- 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra
- 'XAH_CTRL_1_Res': '$c0', # Reserved Bit
- 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames
- 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames
- 'XAH_CTRL_1_Res': '$8', # Reserved Bit
- 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time
- 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode
- 'XAH_CTRL_1_Res': '$1', # Reserved Bit
- 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont
- 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt
- 'PLL_CF' : '$15a', # Transceiver Center Frequency C
- 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra
- 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra
- 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration
- 'PART_NUM' : '$15c', # Device Identification Register
- 'PART_NUM_PART_NUM': '$ff', # Part Number
- 'VERSION_NUM' : '$15d', # Device Identification Register
- 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number
- 'MAN_ID_0' : '$15e', # Device Identification Register
- 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte)
- 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte)
- 'MAN_ID_1' : '$15f', # Device Identification Register
- 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte)
- 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address
- 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address
- 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address
- 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address
- 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw
- 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID
- 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID
- 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw
- 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID
- 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address
- 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address
- 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R
- 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address
- 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating
- 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra
- 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc
- 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment
- 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num
- 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num
- 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num
- 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra
- 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo
- 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field
- 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T
- 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor
- 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num
- 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E
- 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent
- 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent
- 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr
- 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist
- 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len
- 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length
- 'TRXFBST' : '$180', # Start of frame buffer
- 'TRXFBEND' : '$1ff', # End of frame buffer
-
-# Module SYMCNT
- 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare
- 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare
- 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare
- 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare
- 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare
- 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare
- 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare
- 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare
- 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare
- 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare
- 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare
- 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare
- 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare
- 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare
- 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp
- 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp
- 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp
- 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp
- 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp
- 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp
- 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam
- 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam
- 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam
- 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam
- 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam
- 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam
- 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt
- 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt
- 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt
- 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt
- 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt
- 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt
- 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt
- 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt
- 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu
- 'SCIRQS_Res': '$e0', # Reserved Bit
- 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ
- 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ
- 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I
- 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask
- 'SCIRQM_Res': '$e0', # Reserved Bit
- 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl
- 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en
- 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3
- 'SCSR' : '$de', # Symbol Counter Status Register
- 'SCSR_Res': '$fe', # Reserved Bit
- 'SCSR_SCBSY': '$1', # Symbol Counter busy
- 'SCCR1' : '$dd', # Symbol Counter Control Registe
- 'SCCR1_Res': '$fe', # Reserved Bit
- 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable
- 'SCCR0' : '$dc', # Symbol Counter Control Registe
- 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization
- 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp
- 'SCCR0_SCEN': '$20', # Symbol Counter enable
- 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se
- 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times
- 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_Res': '$c0', # Reserved
- 'EECR_EEPM': '$30', # EEPROM Programming Mode
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Programming Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Register
- 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con
- 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con
- 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con
- 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con
- 'EICRB' : '$6a', # External Interrupt Control Reg
- 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con
- 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con
- 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con
- 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$ff', # External Interrupt Request Ena
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$ff', # External Interrupt Flag
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_Res': '$f8', # Reserved Bit
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_Res': '$f8', # Reserved Bit
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC Multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status Reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status Reg
- 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ADCSRB_REFOK': '$20', # Reference Voltage OK
- 'ADCSRB_ACCH': '$10', # Analog Channel Change
- 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source
- 'ADCSRC' : '$77', # The ADC Control and Status Reg
- 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time
- 'ADCSRC_Res0': '$20', # Reserved
- 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time
- 'DIDR2' : '$7d', # Digital Input Disable Register
- 'DIDR2_ADC15D': '$80', # Reserved Bits
- 'DIDR2_ADC14D': '$40', # Reserved Bits
- 'DIDR2_ADC13D': '$20', # Reserved Bits
- 'DIDR2_ADC12D': '$10', # Reserved Bits
- 'DIDR2_ADC11D': '$8', # Reserved Bits
- 'DIDR2_ADC10D': '$4', # Reserved Bits
- 'DIDR2_ADC9D': '$2', # Reserved Bits
- 'DIDR2_ADC8D': '$1', # Reserved Bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input
- 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_Res': '$60', # Reserved
- 'MCUCR_PUD': '$10', # Pull-up Disable
- 'MCUCR_Res': '$c', # Reserved
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_Res': '$e0', # Reserved
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on Reset Flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_Res': '$70', # Reserved
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_Res': '$f0', # Reserved
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'RAMPZ' : '$5b', # Extended Z-pointer Register fo
- 'RAMPZ_Res': '$fc', # Reserved
- 'RAMPZ_RAMPZ': '$3', # Extended Z-Pointer Value
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0
- 'PRR2' : '$63', # Power Reduction Register 2
- 'PRR2_Res': '$f0', # Reserved Bit
- 'PRR2_PRRAM': '$f', # Power Reduction SRAMs
- 'PRR1' : '$65', # Power Reduction Register 1
- 'PRR1_Res': '$80', # Reserved Bit
- 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver
- 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
- 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
- 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
- 'PRR1_PRUSART': '$7', # Reserved
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRPGA': '$10', # Power Reduction PGA
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRUSART0': '$2', # Power Reduction USART
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
-# Module FLASH
- 'NEMCR' : '$75', # Flash Extended-Mode Control-Re
- 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f
- 'NEMCR_AEAM': '$30', # Address for Extended Address M
- 'BGCR' : '$67', # Reference Voltage Calibration
- 'BGCR_Res': '$80', # Reserved Bit
- 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits
- 'BGCR_BGCAL': '$7', # Coarse Calibration Bits
-
-# Module PWRCTRL
- 'TRXPR' : '$139', # Transceiver Pin Register
- 'TRXPR_Res': '$f0', # Reserved
- 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont
- 'TRXPR_TRXRST': '$1', # Force Transceiver Reset
- 'DRTRAM0' : '$135', # Data Retention Configuration R
- 'DRTRAM0_Res': '$c0', # Reserved
- 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM1' : '$134', # Data Retention Configuration R
- 'DRTRAM1_Res': '$c0', # Reserved
- 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM2' : '$133', # Data Retention Configuration R
- 'DRTRAM2_Res': '$40', # Reserved Bit
- 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention
- 'DRTRAM3' : '$132', # Data Retention Configuration R
- 'DRTRAM3_Res': '$c0', # Reserved
- 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK
- 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention
- 'LLDRL' : '$130', # Low Leakage Voltage Regulator
- 'LLDRL_Res': '$f0', # Reserved
- 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits
- 'LLDRH' : '$131', # Low Leakage Voltage Regulator
- 'LLDRH_Res': '$e0', # Reserved
- 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits
- 'LLCR' : '$12f', # Low Leakage Voltage Regulator
- 'LLCR_Res': '$c0', # Reserved Bit
- 'LLCR_LLDONE': '$20', # Calibration Done
- 'LLCR_LLCOMP': '$10', # Comparator Output
- 'LLCR_LLCAL': '$8', # Calibration Active
- 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur
- 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui
- 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration
- 'DPDS0' : '$136', # Port Driver Strength Register
- 'DPDS0_PFDRV': '$c0', # Driver Strength Port F
- 'DPDS0_PEDRV': '$30', # Driver Strength Port E
- 'DPDS0_PDDRV': '$c', # Driver Strength Port D
- 'DPDS0_PBDRV': '$3', # Driver Strength Port B
- 'DPDS1' : '$137', # Port Driver Strength Register
- 'DPDS1_Res': '$fc', # Reserved
- 'DPDS1_PGDRV': '$3', # Driver Strength Port G
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', # Pull-up Disable
-
-# Module USART0_SPI
- 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmit Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu
- 'UCSR0C_UDORD0': '$4', # Data Order
- 'UCSR0C_UCPHA0': '$2', # Clock Phase
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
-
-# Module USART1_SPI
- 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmit Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu
- 'UCSR1C_UDORD1': '$4', # Data Order
- 'UCSR1C_UCPHA1': '$2', # Clock Phase
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega128rfa1/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega128rfa1/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega128rfa1/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega128rfa1/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT