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-rw-r--r--amforth-6.5/avr8/devices/atmega164a/atmega164a.frt347
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt47
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt27
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt21
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt91
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt17
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt35
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt11
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt29
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt42
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt47
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt57
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt34
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt51
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt51
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt15
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/device.asm120
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/device.inc1128
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/device.py387
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/words/sleep.asm19
26 files changed, 0 insertions, 2652 deletions
diff --git a/amforth-6.5/avr8/devices/atmega164a/atmega164a.frt b/amforth-6.5/avr8/devices/atmega164a/atmega164a.frt
deleted file mode 100644
index 52631ae..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/atmega164a.frt
+++ /dev/null
@@ -1,347 +0,0 @@
-\ Partname: ATmega164A
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&123 constant ADCSRB \ ADC Control and Status Register B
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ PORTA
-&34 constant PORTA \ Port A Data Register
-&33 constant DDRA \ Port A Data Direction Register
-&32 constant PINA \ Port A Input Pins
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ JTAG
-&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
-&85 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
-&84 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $07 constant EIFR_INTF \ External Interrupt Flags
-&115 constant PCMSK3 \ Pin Change Mask Register 3
- $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- $40 constant DIDR0_ADC6D \
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
- $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
- $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- $07 constant TCCR1B_CS1 \ Clock Select1 bits
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ SPI
-&78 constant SPDR0 \ SPI Data Register
-&77 constant SPSR0 \ SPI Status Register
- $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
- $40 constant SPSR0_WCOL0 \ Write Collision Flag
- $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
-&76 constant SPCR0 \ SPI Control Register
- $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
- $40 constant SPCR0_SPE0 \ SPI Enable
- $20 constant SPCR0_DORD0 \ Data Order
- $10 constant SPCR0_MSTR0 \ Master/Slave Select
- $08 constant SPCR0_CPOL0 \ Clock polarity
- $04 constant SPCR0_CPHA0 \ Clock Phase
- $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
- $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&100 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
- $01 constant PRR0_PRADC \ Power Reduction ADC
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
-&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
-&16 constant WDTAddr \ Watchdog Time-out Interrupt
-&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
-&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&40 constant USART0__RXAddr \ USART0, Rx Complete
-&42 constant USART0__UDREAddr \ USART0 Data register Empty
-&44 constant USART0__TXAddr \ USART0, Tx Complete
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant ADCAddr \ ADC Conversion Complete
-&50 constant EE_READYAddr \ EEPROM Ready
-&52 constant TWIAddr \ 2-wire Serial Interface
-&54 constant SPM_READYAddr \ Store Program Memory Read
-&56 constant USART1_RXAddr \ USART1 RX complete
-&58 constant USART1_UDREAddr \ USART1 Data Register Empty
-&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt
deleted file mode 100644
index 12944ca..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt
+++ /dev/null
@@ -1,47 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ AD_CONVERTER
-$7c constant ADMUX \ The ADC multiplexer Selection
- $c0 constant ADMUX_REFS \ Reference Selection Bits
- 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- 7c $20 bitmask: ADMUX.ADLAR \ Left Adjust Result
- $1f constant ADMUX_MUX \ Analog Channel and Gain Select
- 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
-$78 constant ADC \ ADC Data Register Bytes
-$7a constant ADCSRA \ The ADC Control and Status reg
- $80 constant ADCSRA_ADEN \ ADC Enable
- 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
- $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
- 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
- $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
- 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
-$7b constant ADCSRB \ The ADC Control and Status reg
- $40 constant ADCSRB_ACME \
- 7b $40 bitmask: ADCSRB.ACME \
- $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
- 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source bits
-$7e constant DIDR0 \ Digital Input Disable Register
- $80 constant DIDR0_ADC7D \
- 7e $80 bitmask: DIDR0.ADC7D \
- $40 constant DIDR0_ADC6D \
- 7e $40 bitmask: DIDR0.ADC6D \
- $20 constant DIDR0_ADC5D \
- 7e $20 bitmask: DIDR0.ADC5D \
- $10 constant DIDR0_ADC4D \
- 7e $10 bitmask: DIDR0.ADC4D \
- $8 constant DIDR0_ADC3D \
- 7e $8 bitmask: DIDR0.ADC3D \
- $4 constant DIDR0_ADC2D \
- 7e $4 bitmask: DIDR0.ADC2D \
- $2 constant DIDR0_ADC1D \
- 7e $2 bitmask: DIDR0.ADC1D \
- $1 constant DIDR0_ADC0D \
- 7e $1 bitmask: DIDR0.ADC0D \
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt
deleted file mode 100644
index b7caf2f..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt
+++ /dev/null
@@ -1,27 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ ANALOG_COMPARATOR
-$7b constant ADCSRB \ ADC Control and Status Registe
- $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
- 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
-$50 constant ACSR \ Analog Comparator Control And
- $80 constant ACSR_ACD \ Analog Comparator Disable
- 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
- 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
- $20 constant ACSR_ACO \ Analog Compare Output
- 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
- 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
- $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
- 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
- $4 constant ACSR_ACIC \ Analog Comparator Input Captur
- 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
- $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
- 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
-$7f constant DIDR1 \ Digital Input Disable Register
- $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
- $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
- 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt
deleted file mode 100644
index d229c7f..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt
+++ /dev/null
@@ -1,21 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ BOOT_LOAD
-$57 constant SPMCSR \ Store Program Memory Control R
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read
- 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write section read
- $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
- $4 constant SPMCSR_PGWRT \ Page Write
- 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
- $2 constant SPMCSR_PGERS \ Page Erase
- 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
- $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
- 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt
deleted file mode 100644
index bbf9d5c..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt
+++ /dev/null
@@ -1,91 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ CPU
-$5f constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- 5f $80 bitmask: SREG.I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- 5f $40 bitmask: SREG.T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- 5f $20 bitmask: SREG.H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- 5f $10 bitmask: SREG.S \ Sign Bit
- $8 constant SREG_V \ Two's Complement Overflow Flag
- 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
- $4 constant SREG_N \ Negative Flag
- 5f $4 bitmask: SREG.N \ Negative Flag
- $2 constant SREG_Z \ Zero Flag
- 5f $2 bitmask: SREG.Z \ Zero Flag
- $1 constant SREG_C \ Carry Flag
- 5f $1 bitmask: SREG.C \ Carry Flag
-$5d constant SP \ Stack Pointer
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
- $10 constant MCUCR_PUD \ Pull-up disable
- 55 $10 bitmask: MCUCR.PUD \ Pull-up disable
- $2 constant MCUCR_IVSEL \ Interrupt Vector Select
- 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
- $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
- 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
- $8 constant MCUSR_WDRF \ Watchdog Reset Flag
- 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
- $4 constant MCUSR_BORF \ Brown-out Reset Flag
- 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
- $2 constant MCUSR_EXTRF \ External Reset Flag
- 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
- $1 constant MCUSR_PORF \ Power-on reset flag
- 54 $1 bitmask: MCUSR.PORF \ Power-on reset flag
-$66 constant OSCCAL \ Oscillator Calibration Value
-$61 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- 61 $80 bitmask: CLKPR.CLKPCE \
- $f constant CLKPR_CLKPS \
- 61 $f bitmask: CLKPR.CLKPS \
-$53 constant SMCR \ Sleep Mode Control Register
- $e constant SMCR_SM \ Sleep Mode Select bits
- 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
- $1 constant SMCR_SE \ Sleep Enable
- 53 $1 bitmask: SMCR.SE \ Sleep Enable
-$4b constant GPIOR2 \ General Purpose IO Register 2
- $ff constant GPIOR2_GPIOR \ General Purpose IO Register 2
- 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose IO Register 2
-$4a constant GPIOR1 \ General Purpose IO Register 1
- $ff constant GPIOR1_GPIOR \ General Purpose IO Register 1
- 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose IO Register 1
-$3e constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0
- 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose IO Register 0
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0
- 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose IO Register 0
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0
- 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose IO Register 0
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0
- 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose IO Register 0
- $8 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0
- 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose IO Register 0
- $4 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0
- 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose IO Register 0
- $2 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0
- 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose IO Register 0
- $1 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0
- 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose IO Register 0
-$64 constant PRR0 \ Power Reduction Register0
- $80 constant PRR0_PRTWI \ Power Reduction TWI
- 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
- $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
- 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
- $12 constant PRR0_PRUSART \ Power Reduction USARTs
- 64 $12 bitmask: PRR0.PRUSART \ Power Reduction USARTs
- $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
- $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
- 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
- $1 constant PRR0_PRADC \ Power Reduction ADC
- 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt
deleted file mode 100644
index b18c275..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt
+++ /dev/null
@@ -1,17 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ EEPROM
-$41 constant EEAR \ EEPROM Address Register Low By
-$40 constant EEDR \ EEPROM Data Register
-$3f constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode Bits
- $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
- $4 constant EECR_EEMPE \ EEPROM Master Write Enable
- 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
- $2 constant EECR_EEPE \ EEPROM Write Enable
- 3f $2 bitmask: EECR.EEPE \ EEPROM Write Enable
- $1 constant EECR_EERE \ EEPROM Read Enable
- 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt
deleted file mode 100644
index 13ed947..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt
+++ /dev/null
@@ -1,35 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ EXTERNAL_INTERRUPT
-$69 constant EICRA \ External Interrupt Control Reg
- $30 constant EICRA_ISC2 \ External Interrupt Sense Contr
- 69 $30 bitmask: EICRA.ISC2 \ External Interrupt Sense Contr
- $c constant EICRA_ISC1 \ External Interrupt Sense Contr
- 69 $c bitmask: EICRA.ISC1 \ External Interrupt Sense Contr
- $3 constant EICRA_ISC0 \ External Interrupt Sense Contr
- 69 $3 bitmask: EICRA.ISC0 \ External Interrupt Sense Contr
-$3d constant EIMSK \ External Interrupt Mask Regist
- $7 constant EIMSK_INT \ External Interrupt Request 2 E
- 3d $7 bitmask: EIMSK.INT \ External Interrupt Request 2 E
-$3c constant EIFR \ External Interrupt Flag Regist
- $7 constant EIFR_INTF \ External Interrupt Flags
- 3c $7 bitmask: EIFR.INTF \ External Interrupt Flags
-$73 constant PCMSK3 \ Pin Change Mask Register 3
- $ff constant PCMSK3_PCINT \ Pin Change Enable Masks
- 73 $ff bitmask: PCMSK3.PCINT \ Pin Change Enable Masks
-$6d constant PCMSK2 \ Pin Change Mask Register 2
- $ff constant PCMSK2_PCINT \ Pin Change Enable Masks
- 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Masks
-$6c constant PCMSK1 \ Pin Change Mask Register 1
- $ff constant PCMSK1_PCINT \ Pin Change Enable Masks
- 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Masks
-$6b constant PCMSK0 \ Pin Change Mask Register 0
- $ff constant PCMSK0_PCINT \ Pin Change Enable Masks
- 6b $ff bitmask: PCMSK0.PCINT \ Pin Change Enable Masks
-$3b constant PCIFR \ Pin Change Interrupt Flag Regi
- $f constant PCIFR_PCIF \ Pin Change Interrupt Flags
- 3b $f bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
-$68 constant PCICR \ Pin Change Interrupt Control R
- $f constant PCICR_PCIE \ Pin Change Interrupt Enables
- 68 $f bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt
deleted file mode 100644
index cd82742..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt
+++ /dev/null
@@ -1,11 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ JTAG
-$51 constant OCDR \ On-Chip Debug Related Register
-$55 constant MCUCR \ MCU Control Register
- $80 constant MCUCR_JTD \ JTAG Interface Disable
- 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
-$54 constant MCUSR \ MCU Status Register
- $10 constant MCUSR_JTRF \ JTAG Reset Flag
- 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt
deleted file mode 100644
index afbaa67..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ PORTA
-$22 constant PORTA \ Port A Data Register
-$21 constant DDRA \ Port A Data Direction Register
-$20 constant PINA \ Port A Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt
deleted file mode 100644
index 0ec791c..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ PORTB
-$25 constant PORTB \ Port B Data Register
-$24 constant DDRB \ Port B Data Direction Register
-$23 constant PINB \ Port B Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt
deleted file mode 100644
index 9855199..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ PORTC
-$28 constant PORTC \ Port C Data Register
-$27 constant DDRC \ Port C Data Direction Register
-$26 constant PINC \ Port C Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt
deleted file mode 100644
index 9015b02..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt
+++ /dev/null
@@ -1,7 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ PORTD
-$2b constant PORTD \ Port D Data Register
-$2a constant DDRD \ Port D Data Direction Register
-$29 constant PIND \ Port D Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt
deleted file mode 100644
index c548ee9..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt
+++ /dev/null
@@ -1,29 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ SPI
-$4e constant SPDR0 \ SPI Data Register
-$4d constant SPSR0 \ SPI Status Register
- $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
- 4d $80 bitmask: SPSR0.SPIF0 \ SPI Interrupt Flag
- $40 constant SPSR0_WCOL0 \ Write Collision Flag
- 4d $40 bitmask: SPSR0.WCOL0 \ Write Collision Flag
- $1 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
- 4d $1 bitmask: SPSR0.SPI2X0 \ Double SPI Speed Bit
-$4c constant SPCR0 \ SPI Control Register
- $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
- 4c $80 bitmask: SPCR0.SPIE0 \ SPI Interrupt Enable
- $40 constant SPCR0_SPE0 \ SPI Enable
- 4c $40 bitmask: SPCR0.SPE0 \ SPI Enable
- $20 constant SPCR0_DORD0 \ Data Order
- 4c $20 bitmask: SPCR0.DORD0 \ Data Order
- $10 constant SPCR0_MSTR0 \ Master/Slave Select
- 4c $10 bitmask: SPCR0.MSTR0 \ Master/Slave Select
- $8 constant SPCR0_CPOL0 \ Clock polarity
- 4c $8 bitmask: SPCR0.CPOL0 \ Clock polarity
- $4 constant SPCR0_CPHA0 \ Clock Phase
- 4c $4 bitmask: SPCR0.CPHA0 \ Clock Phase
- $2 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
- 4c $2 bitmask: SPCR0.SPR10 \ SPI Clock Rate Select 1
- $1 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
- 4c $1 bitmask: SPCR0.SPR00 \ SPI Clock Rate Select 0
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt
deleted file mode 100644
index c2de345..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt
+++ /dev/null
@@ -1,42 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_0
-$48 constant OCR0B \ Timer/Counter0 Output Compare
-$47 constant OCR0A \ Timer/Counter0 Output Compare
-$46 constant TCNT0 \ Timer/Counter0
-$45 constant TCCR0B \ Timer/Counter Control Register
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
- $8 constant TCCR0B_WGM02 \
- 45 $8 bitmask: TCCR0B.WGM02 \
- $7 constant TCCR0B_CS0 \ Clock Select
- 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
-$44 constant TCCR0A \ Timer/Counter Control Registe
- $c0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Cor
- 44 $c0 bitmask: TCCR0A.COM0A \ Compare Output Mode, Phase Cor
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- 44 $30 bitmask: TCCR0A.COM0B \ Compare Output Mode, Fast PWm
- $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
- 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
-$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
- $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
- 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
- $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
- 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
- $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
- 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
-$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
- $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
- 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
- $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
- 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
- $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
- 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
-$43 constant GTCCR \ General Timer/Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $1 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1
- 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset Timer/Counter1
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt
deleted file mode 100644
index 43e5db2..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt
+++ /dev/null
@@ -1,47 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_1
-$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
- 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
- $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
- 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
- $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
- 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
- $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
- 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
-$36 constant TIFR1 \ Timer/Counter Interrupt Flag r
- $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
- 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
- $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
- 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
- $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
- 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
- $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
- 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
-$80 constant TCCR1A \ Timer/Counter1 Control Registe
- $c0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode 1B, bits
- $3 constant TCCR1A_WGM1 \ Pulse Width Modulator Select B
- 80 $3 bitmask: TCCR1A.WGM1 \ Pulse Width Modulator Select B
-$81 constant TCCR1B \ Timer/Counter1 Control Registe
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
- 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode Bits
- $7 constant TCCR1B_CS1 \ Clock Select1 bits
- 81 $7 bitmask: TCCR1B.CS1 \ Clock Select1 bits
-$82 constant TCCR1C \ Timer/Counter1 Control Registe
- $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
- 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
- $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
- 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
-$84 constant TCNT1 \ Timer/Counter1 Bytes
-$88 constant OCR1A \ Timer/Counter1 Output Compare
-$8a constant OCR1B \ Timer/Counter1 Output Compare
-$86 constant ICR1 \ Timer/Counter1 Input Capture R
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt
deleted file mode 100644
index 2dd0720..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt
+++ /dev/null
@@ -1,57 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ TIMER_COUNTER_2
-$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
- $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
- 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
- $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
- 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
- $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
- 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
-$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
- $4 constant TIFR2_OCF2B \ Output Compare Flag 2B
- 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2B
- $2 constant TIFR2_OCF2A \ Output Compare Flag 2A
- 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2A
- $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
- 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
-$b0 constant TCCR2A \ Timer/Counter2 Control Registe
- $c0 constant TCCR2A_COM2A \ Compare Output Mode bits
- b0 $c0 bitmask: TCCR2A.COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- b0 $30 bitmask: TCCR2A.COM2B \ Compare Output Mode bits
- $3 constant TCCR2A_WGM2 \ Waveform Genration Mode
- b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Genration Mode
-$b1 constant TCCR2B \ Timer/Counter2 Control Registe
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
- $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
- b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
- $7 constant TCCR2B_CS2 \ Clock Select bits
- b1 $7 bitmask: TCCR2B.CS2 \ Clock Select bits
-$b2 constant TCNT2 \ Timer/Counter2
-$b4 constant OCR2B \ Timer/Counter2 Output Compare
-$b3 constant OCR2A \ Timer/Counter2 Output Compare
-$b6 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- b6 $20 bitmask: ASSR.AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
- $8 constant ASSR_OCR2AUB \ Output Compare Register2 Updat
- b6 $8 bitmask: ASSR.OCR2AUB \ Output Compare Register2 Updat
- $4 constant ASSR_OCR2BUB \ Output Compare Register 2 Upda
- b6 $4 bitmask: ASSR.OCR2BUB \ Output Compare Register 2 Upda
- $2 constant ASSR_TCR2AUB \ Timer/Counter Control Register
- b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter Control Register
- $1 constant ASSR_TCR2BUB \ Timer/Counter Control Register
- b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter Control Register
-$43 constant GTCCR \ General Timer Counter Control
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization
- 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
- $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
- 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt
deleted file mode 100644
index d30b667..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt
+++ /dev/null
@@ -1,34 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ TWI
-$bd constant TWAMR \ TWI (Slave) Address Mask Regis
- $fe constant TWAMR_TWAM \
- bd $fe bitmask: TWAMR.TWAM \
-$b8 constant TWBR \ TWI Bit Rate register
-$bc constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- bc $20 bitmask: TWCR.TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- bc $10 bitmask: TWCR.TWSTO \ TWI Stop Condition Bit
- $8 constant TWCR_TWWC \ TWI Write Collition Flag
- bc $8 bitmask: TWCR.TWWC \ TWI Write Collition Flag
- $4 constant TWCR_TWEN \ TWI Enable Bit
- bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
- $1 constant TWCR_TWIE \ TWI Interrupt Enable
- bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
-$b9 constant TWSR \ TWI Status Register
- $f8 constant TWSR_TWS \ TWI Status
- b9 $f8 bitmask: TWSR.TWS \ TWI Status
- $3 constant TWSR_TWPS \ TWI Prescaler
- b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler
-$bb constant TWDR \ TWI Data register
-$ba constant TWAR \ TWI (Slave) Address register
- $fe constant TWAR_TWA \ TWI (Slave) Address register B
- ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address register B
- $1 constant TWAR_TWGCE \ TWI General Call Recognition E
- ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt
deleted file mode 100644
index ae51362..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ USART0
-$c6 constant UDR0 \ USART I/O Data Register
-$c0 constant UCSR0A \ USART Control and Status Regis
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- c0 $10 bitmask: UCSR0A.FE0 \ Framing Error
- $8 constant UCSR0A_DOR0 \ Data overRun
- c0 $8 bitmask: UCSR0A.DOR0 \ Data overRun
- $4 constant UCSR0A_UPE0 \ Parity Error
- c0 $4 bitmask: UCSR0A.UPE0 \ Parity Error
- $2 constant UCSR0A_U2X0 \ Double the USART transmission
- c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART transmission
- $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
- c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
-$c1 constant UCSR0B \ USART Control and Status Regis
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Inte
- c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data register Empty Inte
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
- $8 constant UCSR0B_TXEN0 \ Transmitter Enable
- c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
- $4 constant UCSR0B_UCSZ02 \ Character Size
- c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
- $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
- c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
- $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
- c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
-$c2 constant UCSR0C \ USART Control and Status Regis
- $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
- c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode Bits
- $8 constant UCSR0C_USBS0 \ Stop Bit Select
- c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
- $6 constant UCSR0C_UCSZ0 \ Character Size
- c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
- $1 constant UCSR0C_UCPOL0 \ Clock Polarity
- c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
-$c4 constant UBRR0 \ USART Baud Rate Register Byte
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt
deleted file mode 100644
index 6bb4ff9..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt
+++ /dev/null
@@ -1,51 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ USART1
-$ce constant UDR1 \ USART I/O Data Register
-$c8 constant UCSR1A \ USART Control and Status Regis
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- c8 $10 bitmask: UCSR1A.FE1 \ Framing Error
- $8 constant UCSR1A_DOR1 \ Data overRun
- c8 $8 bitmask: UCSR1A.DOR1 \ Data overRun
- $4 constant UCSR1A_UPE1 \ Parity Error
- c8 $4 bitmask: UCSR1A.UPE1 \ Parity Error
- $2 constant UCSR1A_U2X1 \ Double the USART transmission
- c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART transmission
- $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
- c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
-$c9 constant UCSR1B \ USART Control and Status Regis
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Inte
- c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data register Empty Inte
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
- $8 constant UCSR1B_TXEN1 \ Transmitter Enable
- c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
- $4 constant UCSR1B_UCSZ12 \ Character Size
- c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
- $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
- c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
- $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
- c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
-$ca constant UCSR1C \ USART Control and Status Regis
- $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
- ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode Bits
- $8 constant UCSR1C_USBS1 \ Stop Bit Select
- ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
- $6 constant UCSR1C_UCSZ1 \ Character Size
- ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
- $1 constant UCSR1C_UCPOL1 \ Clock Polarity
- ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
-$cc constant UBRR1 \ USART Baud Rate Register Byte
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt
deleted file mode 100644
index 3dc985f..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt
+++ /dev/null
@@ -1,15 +0,0 @@
-\ Generated automatically for atmega164a
-\ #require bitnames.frt
-
-\ WATCHDOG
-$60 constant WDTCSR \ Watchdog Timer Control Registe
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
- 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
- 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
- $8 constant WDTCSR_WDE \ Watch Dog Enable
- 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/atmega164a/device.asm b/amforth-6.5/avr8/devices/atmega164a/device.asm
deleted file mode 100644
index dc12da8..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/device.asm
+++ /dev/null
@@ -1,120 +0,0 @@
-; Partname: ATmega164A
-; generated automatically, do not edit
-
-.nolist
- .include "m164Adef.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_USART0 = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_JTAG = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_EEPROM = 0
-.set WANT_SPI = 0
-.set WANT_TWI = 0
-.set WANT_USART1 = 0
-.set WANT_CPU = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Pin Change Interrupt Request 2
-.org 14
- rcall isr ; Pin Change Interrupt Request 3
-.org 16
- rcall isr ; Watchdog Time-out Interrupt
-.org 18
- rcall isr ; Timer/Counter2 Compare Match A
-.org 20
- rcall isr ; Timer/Counter2 Compare Match B
-.org 22
- rcall isr ; Timer/Counter2 Overflow
-.org 24
- rcall isr ; Timer/Counter1 Capture Event
-.org 26
- rcall isr ; Timer/Counter1 Compare Match A
-.org 28
- rcall isr ; Timer/Counter1 Compare Match B
-.org 30
- rcall isr ; Timer/Counter1 Overflow
-.org 32
- rcall isr ; Timer/Counter0 Compare Match A
-.org 34
- rcall isr ; Timer/Counter0 Compare Match B
-.org 36
- rcall isr ; Timer/Counter0 Overflow
-.org 38
- rcall isr ; SPI Serial Transfer Complete
-.org 40
- rcall isr ; USART0, Rx Complete
-.org 42
- rcall isr ; USART0 Data register Empty
-.org 44
- rcall isr ; USART0, Tx Complete
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; ADC Conversion Complete
-.org 50
- rcall isr ; EEPROM Ready
-.org 52
- rcall isr ; 2-wire Serial Interface
-.org 54
- rcall isr ; Store Program Memory Read
-.org 56
- rcall isr ; USART1 RX complete
-.org 58
- rcall isr ; USART1 Data Register Empty
-.org 60
- rcall isr ; USART1 TX complete
-.equ INTVECTORS = 31
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 31
-mcu_name:
- .dw 10
- .db "ATmega164A"
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega164a/device.inc b/amforth-6.5/avr8/devices/atmega164a/device.inc
deleted file mode 100644
index 79c054f..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega164A
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Control and Status Register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_PORTA == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw 34
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw 32
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_JTAG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; On-Chip Debug Related Register in I/O Memory
-VE_OCDR:
- .dw $ff04
- .db "OCDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCDR
-XT_OCDR:
- .dw PFA_DOVARIABLE
-PFA_OCDR:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 3
-VE_PCMSK3:
- .dw $ff06
- .db "PCMSK3"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK3
-XT_PCMSK3:
- .dw PFA_DOVARIABLE
-PFA_PCMSK3:
- .dw 115
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR0:
- .dw $ff05
- .db "SPDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR0
-XT_SPDR0:
- .dw PFA_DOVARIABLE
-PFA_SPDR0:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR0:
- .dw $ff05
- .db "SPSR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR0
-XT_SPSR0:
- .dw PFA_DOVARIABLE
-PFA_SPSR0:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR0:
- .dw $ff05
- .db "SPCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR0
-XT_SPCR0:
- .dw PFA_DOVARIABLE
-PFA_SPCR0:
- .dw 76
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega164a/device.py b/amforth-6.5/avr8/devices/atmega164a/device.py
deleted file mode 100644
index ea2ebc4..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/device.py
+++ /dev/null
@@ -1,387 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega164A
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'INT2Addr' : '#6', # External Interrupt Request 2
- 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
- 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
- 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
- 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
- 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
- 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
- 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
- 'USART0_RXAddr' : '#40', # USART0, Rx Complete
- 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
- 'USART0_TXAddr' : '#44', # USART0, Tx Complete
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'ADCAddr' : '#48', # ADC Conversion Complete
- 'EE_READYAddr' : '#50', # EEPROM Ready
- 'TWIAddr' : '#52', # 2-wire Serial Interface
- 'SPM_READYAddr' : '#54', # Store Program Memory Read
- 'USART1_RXAddr' : '#56', # USART1 RX complete
- 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
- 'USART1_TXAddr' : '#60', # USART1 TX complete
-
-# Module ANALOG_COMPARATOR
- 'ADCSRB' : '$7b', # ADC Control and Status Registe
- 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module PORTA
- 'PORTA' : '$22', # Port A Data Register
- 'DDRA' : '$21', # Port A Data Direction Register
- 'PINA' : '$20', # Port A Input Pins
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module JTAG
- 'OCDR' : '$51', # On-Chip Debug Related Register
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
-
-# Module BOOT_LOAD
- 'SPMCSR' : '$57', # Store Program Memory Control R
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
- 'SPMCSR_SIGRD': '$20', # Signature Row Read
- 'SPMCSR_RWWSRE': '$10', # Read While Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$7', # External Interrupt Request 2 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$7', # External Interrupt Flags
- 'PCMSK3' : '$73', # Pin Change Mask Register 3
- 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC7D': '$80', #
- 'DIDR0_ADC6D': '$40', #
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
- 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
- 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
- 'TCCR1B_CS1': '$7', # Clock Select1 bits
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
- 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Low By
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
-# Module SPI
- 'SPDR0' : '$4e', # SPI Data Register
- 'SPSR0' : '$4d', # SPI Status Register
- 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
- 'SPSR0_WCOL0': '$40', # Write Collision Flag
- 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
- 'SPCR0' : '$4c', # SPI Control Register
- 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
- 'SPCR0_SPE0': '$40', # SPI Enable
- 'SPCR0_DORD0': '$20', # Data Order
- 'SPCR0_MSTR0': '$10', # Master/Slave Select
- 'SPCR0_CPOL0': '$8', # Clock polarity
- 'SPCR0_CPHA0': '$4', # Clock Phase
- 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
- 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module USART1
- 'UDR1' : '$ce', # USART I/O Data Register
- 'UCSR1A' : '$c8', # USART Control and Status Regis
- 'UCSR1A_RXC1': '$80', # USART Receive Complete
- 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
- 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
- 'UCSR1A_FE1': '$10', # Framing Error
- 'UCSR1A_DOR1': '$8', # Data overRun
- 'UCSR1A_UPE1': '$4', # Parity Error
- 'UCSR1A_U2X1': '$2', # Double the USART transmission
- 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
- 'UCSR1B' : '$c9', # USART Control and Status Regis
- 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
- 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
- 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
- 'UCSR1B_RXEN1': '$10', # Receiver Enable
- 'UCSR1B_TXEN1': '$8', # Transmitter Enable
- 'UCSR1B_UCSZ12': '$4', # Character Size
- 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
- 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
- 'UCSR1C' : '$ca', # USART Control and Status Regis
- 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
- 'UCSR1C_UPM1': '$30', # Parity Mode Bits
- 'UCSR1C_USBS1': '$8', # Stop Bit Select
- 'UCSR1C_UCSZ1': '$6', # Character Size
- 'UCSR1C_UCPOL1': '$1', # Clock Polarity
- 'UBRR1' : '$cc', # USART Baud Rate Register Byte
-
-# Module CPU
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_JTD': '$80', # JTAG Interface Disable
- 'MCUCR_PUD': '$10', # Pull-up disable
- 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
- 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_JTRF': '$10', # JTAG Reset Flag
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', #
- 'CLKPR_CLKPCE': '$80', #
- 'CLKPR_CLKPS': '$f', #
- 'SMCR' : '$53', # Sleep Mode Control Register
- 'SMCR_SM': '$e', # Sleep Mode Select bits
- 'SMCR_SE': '$1', # Sleep Enable
- 'GPIOR2' : '$4b', # General Purpose IO Register 2
- 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
- 'GPIOR1' : '$4a', # General Purpose IO Register 1
- 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
- 'GPIOR0' : '$3e', # General Purpose IO Register 0
- 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
- 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
- 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
- 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
- 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
- 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
- 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
- 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
- 'PRR0' : '$64', # Power Reduction Register0
- 'PRR0_PRTWI': '$80', # Power Reduction TWI
- 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR0_PRUSART': '$12', # Power Reduction USARTs
- 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR0_PRADC': '$1', # Power Reduction ADC
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega164a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega164a/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega164a/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega164a/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega164a/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT