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-rw-r--r--amforth-6.5/avr8/devices/atmega168/atmega168.frt297
-rw-r--r--amforth-6.5/avr8/devices/atmega168/device.asm107
-rw-r--r--amforth-6.5/avr8/devices/atmega168/device.inc996
-rw-r--r--amforth-6.5/avr8/devices/atmega168/device.py322
-rw-r--r--amforth-6.5/avr8/devices/atmega168/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega168/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega168/words/sleep.asm19
7 files changed, 0 insertions, 1789 deletions
diff --git a/amforth-6.5/avr8/devices/atmega168/atmega168.frt b/amforth-6.5/avr8/devices/atmega168/atmega168.frt
deleted file mode 100644
index df0b666..0000000
--- a/amforth-6.5/avr8/devices/atmega168/atmega168.frt
+++ /dev/null
@@ -1,297 +0,0 @@
-\ Partname: ATmega168
-\ generated automatically
-
-\ USART0
-&198 constant UDR0 \ USART I/O Data Register
-&192 constant UCSR0A \ USART Control and Status Register A
- $80 constant UCSR0A_RXC0 \ USART Receive Complete
- $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
- $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
- $10 constant UCSR0A_FE0 \ Framing Error
- $08 constant UCSR0A_DOR0 \ Data overRun
- $04 constant UCSR0A_UPE0 \ Parity Error
- $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
- $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
-&193 constant UCSR0B \ USART Control and Status Register B
- $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
- $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
- $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR0B_RXEN0 \ Receiver Enable
- $08 constant UCSR0B_TXEN0 \ Transmitter Enable
- $04 constant UCSR0B_UCSZ02 \ Character Size
- $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
- $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
-&194 constant UCSR0C \ USART Control and Status Register C
- $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
- $30 constant UCSR0C_UPM0 \ Parity Mode Bits
- $08 constant UCSR0C_USBS0 \ Stop Bit Select
- $06 constant UCSR0C_UCSZ0 \ Character Size
- $01 constant UCSR0C_UCPOL0 \ Clock Polarity
-&196 constant UBRR0 \ USART Baud Rate Register Bytes
-\ TWI
-&189 constant TWAMR \ TWI (Slave) Address Mask Register
- $FE constant TWAMR_TWAM \
-&184 constant TWBR \ TWI Bit Rate register
-&188 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&185 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&187 constant TWDR \ TWI Data register
-&186 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ TIMER_COUNTER_1
-&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter1 Control Register C
- $80 constant TCCR1C_FOC1A \
- $40 constant TCCR1C_FOC1B \
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_2
-&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
- $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
- $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
- $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
-&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
- $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
- $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
- $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
-&176 constant TCCR2A \ Timer/Counter2 Control Register A
- $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
- $30 constant TCCR2A_COM2B \ Compare Output Mode bits
- $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
-&177 constant TCCR2B \ Timer/Counter2 Control Register B
- $80 constant TCCR2B_FOC2A \ Force Output Compare A
- $40 constant TCCR2B_FOC2B \ Force Output Compare B
- $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
- $07 constant TCCR2B_CS2 \ Clock Select bits
-&178 constant TCNT2 \ Timer/Counter2
-&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
-&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
-&182 constant ASSR \ Asynchronous Status Register
- $40 constant ASSR_EXCLK \ Enable External Clock Input
- $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
- $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
- $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
- $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
- $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
-\ AD_CONVERTER
-&124 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&120 constant ADC \ ADC Data Register Bytes
-&122 constant ADCSRA \ The ADC Control and Status register A
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&123 constant ADCSRB \ The ADC Control and Status register B
- $40 constant ADCSRB_ACME \
- $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
-&126 constant DIDR0 \ Digital Input Disable Register
- $20 constant DIDR0_ADC5D \
- $10 constant DIDR0_ADC4D \
- $08 constant DIDR0_ADC3D \
- $04 constant DIDR0_ADC2D \
- $02 constant DIDR0_ADC1D \
- $01 constant DIDR0_ADC0D \
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \ Digital Input Disable Register 1
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTC
-&40 constant PORTC \ Port C Data Register
-&39 constant DDRC \ Port C Data Direction Register
-&38 constant PINC \ Port C Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
-&61 constant EIMSK \ External Interrupt Mask Register
- $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $03 constant EIFR_INTF \ External Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
-&109 constant PCMSK2 \ Pin Change Mask Register 2
- $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-\ SPI
-&78 constant SPDR \ SPI Data Register
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ CPU
-&100 constant PRR \ Power Reduction Register
- $80 constant PRR_PRTWI \ Power Reduction TWI
- $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
- $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
- $02 constant PRR_PRUSART0 \ Power Reduction USART
- $01 constant PRR_PRADC \ Power Reduction ADC
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \ Clock Prescale Register
- $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
- $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&87 constant SPMCSR \ Store Program Memory Control and Status Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \
- $02 constant MCUCR_IVSEL \
- $01 constant MCUCR_IVCE \
-&84 constant MCUSR \ MCU Status Register
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&83 constant SMCR \
- $0E constant SMCR_SM \
- $01 constant SMCR_SE \
-&75 constant GPIOR2 \ General Purpose I/O Register 2
-&74 constant GPIOR1 \ General Purpose I/O Register 1
-&62 constant GPIOR0 \ General Purpose I/O Register 0
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
-&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
-&12 constant WDTAddr \ Watchdog Time-out Interrupt
-&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
-&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
-&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
-&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
-&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
-&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&36 constant USART__RXAddr \ USART Rx Complete
-&38 constant USART__UDREAddr \ USART, Data Register Empty
-&40 constant USART__TXAddr \ USART Tx Complete
-&42 constant ADCAddr \ ADC Conversion Complete
-&44 constant EE_READYAddr \ EEPROM Ready
-&46 constant ANALOG_COMPAddr \ Analog Comparator
-&48 constant TWIAddr \ Two-wire Serial Interface
-&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega168/device.asm b/amforth-6.5/avr8/devices/atmega168/device.asm
deleted file mode 100644
index 74bda58..0000000
--- a/amforth-6.5/avr8/devices/atmega168/device.asm
+++ /dev/null
@@ -1,107 +0,0 @@
-; Partname: ATmega168
-; generated automatically, do not edit
-
-.nolist
- .include "m168def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_USART0 = 0
-.set WANT_TWI = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_SPI = 0
-.set WANT_CPU = 0
-.set WANT_WATCHDOG = 0
-.set WANT_EEPROM = 0
-.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; Pin Change Interrupt Request 0
-.org 8
- rcall isr ; Pin Change Interrupt Request 0
-.org 10
- rcall isr ; Pin Change Interrupt Request 1
-.org 12
- rcall isr ; Watchdog Time-out Interrupt
-.org 14
- rcall isr ; Timer/Counter2 Compare Match A
-.org 16
- rcall isr ; Timer/Counter2 Compare Match A
-.org 18
- rcall isr ; Timer/Counter2 Overflow
-.org 20
- rcall isr ; Timer/Counter1 Capture Event
-.org 22
- rcall isr ; Timer/Counter1 Compare Match A
-.org 24
- rcall isr ; Timer/Counter1 Compare Match B
-.org 26
- rcall isr ; Timer/Counter1 Overflow
-.org 28
- rcall isr ; TimerCounter0 Compare Match A
-.org 30
- rcall isr ; TimerCounter0 Compare Match B
-.org 32
- rcall isr ; Timer/Couner0 Overflow
-.org 34
- rcall isr ; SPI Serial Transfer Complete
-.org 36
- rcall isr ; USART Rx Complete
-.org 38
- rcall isr ; USART, Data Register Empty
-.org 40
- rcall isr ; USART Tx Complete
-.org 42
- rcall isr ; ADC Conversion Complete
-.org 44
- rcall isr ; EEPROM Ready
-.org 46
- rcall isr ; Analog Comparator
-.org 48
- rcall isr ; Two-wire Serial Interface
-.org 50
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 26
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMEN = SELFPRGEN
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 14336
-mcu_numints:
- .dw 26
-mcu_name:
- .dw 9
- .db "ATmega168",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega168/device.inc b/amforth-6.5/avr8/devices/atmega168/device.inc
deleted file mode 100644
index 47d5dcd..0000000
--- a/amforth-6.5/avr8/devices/atmega168/device.inc
+++ /dev/null
@@ -1,996 +0,0 @@
-; Partname: ATmega168
-; generated automatically, no not edit
-
-.if WANT_USART0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR0:
- .dw $ff04
- .db "UDR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR0
-XT_UDR0:
- .dw PFA_DOVARIABLE
-PFA_UDR0:
- .dw 198
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR0A:
- .dw $ff06
- .db "UCSR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0A
-XT_UCSR0A:
- .dw PFA_DOVARIABLE
-PFA_UCSR0A:
- .dw 192
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR0B:
- .dw $ff06
- .db "UCSR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0B
-XT_UCSR0B:
- .dw PFA_DOVARIABLE
-PFA_UCSR0B:
- .dw 193
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR0C:
- .dw $ff06
- .db "UCSR0C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR0C
-XT_UCSR0C:
- .dw PFA_DOVARIABLE
-PFA_UCSR0C:
- .dw 194
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR0:
- .dw $ff05
- .db "UBRR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR0
-XT_UBRR0:
- .dw PFA_DOVARIABLE
-PFA_UBRR0:
- .dw 196
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address Mask Register
-VE_TWAMR:
- .dw $ff05
- .db "TWAMR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAMR
-XT_TWAMR:
- .dw PFA_DOVARIABLE
-PFA_TWAMR:
- .dw 189
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 184
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 188
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 185
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 187
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 186
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask register
-VE_TIMSK2:
- .dw $ff06
- .db "TIMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK2
-XT_TIMSK2:
- .dw PFA_DOVARIABLE
-PFA_TIMSK2:
- .dw 112
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag Register
-VE_TIFR2:
- .dw $ff05
- .db "TIFR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR2
-XT_TIFR2:
- .dw PFA_DOVARIABLE
-PFA_TIFR2:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register A
-VE_TCCR2A:
- .dw $ff06
- .db "TCCR2A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2A
-XT_TCCR2A:
- .dw PFA_DOVARIABLE
-PFA_TCCR2A:
- .dw 176
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register B
-VE_TCCR2B:
- .dw $ff06
- .db "TCCR2B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2B
-XT_TCCR2B:
- .dw PFA_DOVARIABLE
-PFA_TCCR2B:
- .dw 177
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 178
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register B
-VE_OCR2B:
- .dw $ff05
- .db "OCR2B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2B
-XT_OCR2B:
- .dw PFA_DOVARIABLE
-PFA_OCR2B:
- .dw 180
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register A
-VE_OCR2A:
- .dw $ff05
- .db "OCR2A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2A
-XT_OCR2A:
- .dw PFA_DOVARIABLE
-PFA_OCR2A:
- .dw 179
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 182
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 124
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 120
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register A
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 122
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register B
-VE_ADCSRB:
- .dw $ff06
- .db "ADCSRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRB
-XT_ADCSRB:
- .dw PFA_DOVARIABLE
-PFA_ADCSRB:
- .dw 123
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register
-VE_DIDR0:
- .dw $ff05
- .db "DIDR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR0
-XT_DIDR0:
- .dw PFA_DOVARIABLE
-PFA_DIDR0:
- .dw 126
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Digital Input Disable Register 1
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 2
-VE_PCMSK2:
- .dw $ff06
- .db "PCMSK2"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK2
-XT_PCMSK2:
- .dw PFA_DOVARIABLE
-PFA_PCMSK2:
- .dw 109
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register
-VE_PRR:
- .dw $ff03
- .db "PRR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR
-XT_PRR:
- .dw PFA_DOVARIABLE
-PFA_PRR:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-; Clock Prescale Register
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control and Status Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose I/O Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega168/device.py b/amforth-6.5/avr8/devices/atmega168/device.py
deleted file mode 100644
index f2179e8..0000000
--- a/amforth-6.5/avr8/devices/atmega168/device.py
+++ /dev/null
@@ -1,322 +0,0 @@
-# Generated Automatically
-
-# Partname ATmega168
-
-MCUREGS = {
-# Interrupt Vectors
- 'INT0Addr' : '#2', # External Interrupt Request 0
- 'INT1Addr' : '#4', # External Interrupt Request 1
- 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
- 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
- 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
- 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
- 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
- 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
- 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
- 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
- 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
- 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
- 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
- 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
- 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
- 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
- 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
- 'USART_RXAddr' : '#36', # USART Rx Complete
- 'USART_UDREAddr' : '#38', # USART, Data Register Empty
- 'USART_TXAddr' : '#40', # USART Tx Complete
- 'ADCAddr' : '#42', # ADC Conversion Complete
- 'EE_READYAddr' : '#44', # EEPROM Ready
- 'ANALOG_COMPAddr' : '#46', # Analog Comparator
- 'TWIAddr' : '#48', # Two-wire Serial Interface
- 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
-
-# Module USART0
- 'UDR0' : '$c6', # USART I/O Data Register
- 'UCSR0A' : '$c0', # USART Control and Status Regis
- 'UCSR0A_RXC0': '$80', # USART Receive Complete
- 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
- 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
- 'UCSR0A_FE0': '$10', # Framing Error
- 'UCSR0A_DOR0': '$8', # Data overRun
- 'UCSR0A_UPE0': '$4', # Parity Error
- 'UCSR0A_U2X0': '$2', # Double the USART transmission
- 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
- 'UCSR0B' : '$c1', # USART Control and Status Regis
- 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
- 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
- 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
- 'UCSR0B_RXEN0': '$10', # Receiver Enable
- 'UCSR0B_TXEN0': '$8', # Transmitter Enable
- 'UCSR0B_UCSZ02': '$4', # Character Size
- 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
- 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
- 'UCSR0C' : '$c2', # USART Control and Status Regis
- 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
- 'UCSR0C_UPM0': '$30', # Parity Mode Bits
- 'UCSR0C_USBS0': '$8', # Stop Bit Select
- 'UCSR0C_UCSZ0': '$6', # Character Size
- 'UCSR0C_UCPOL0': '$1', # Clock Polarity
- 'UBRR0' : '$c4', # USART Baud Rate Register Byte
-
-# Module TWI
- 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
- 'TWAMR_TWAM': '$fe', #
- 'TWBR' : '$b8', # TWI Bit Rate register
- 'TWCR' : '$bc', # TWI Control Register
- 'TWCR_TWINT': '$80', # TWI Interrupt Flag
- 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
- 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
- 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
- 'TWCR_TWWC': '$8', # TWI Write Collition Flag
- 'TWCR_TWEN': '$4', # TWI Enable Bit
- 'TWCR_TWIE': '$1', # TWI Interrupt Enable
- 'TWSR' : '$b9', # TWI Status Register
- 'TWSR_TWS': '$f8', # TWI Status
- 'TWSR_TWPS': '$3', # TWI Prescaler
- 'TWDR' : '$bb', # TWI Data register
- 'TWAR' : '$ba', # TWI (Slave) Address register
- 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
- 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
-
-# Module TIMER_COUNTER_1
- 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
- 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
- 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
- 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
- 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
- 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
- 'TIFR1_ICF1': '$20', # Input Capture Flag 1
- 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
- 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
- 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
- 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
- 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
- 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
- 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
- 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
- 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
- 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
- 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
- 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
- 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
- 'TCCR1C_FOC1A': '$80', #
- 'TCCR1C_FOC1B': '$40', #
- 'TCNT1' : '$84', # Timer/Counter1 Bytes
- 'OCR1A' : '$88', # Timer/Counter1 Output Compare
- 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
- 'ICR1' : '$86', # Timer/Counter1 Input Capture R
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module TIMER_COUNTER_2
- 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
- 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
- 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
- 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
- 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
- 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
- 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
- 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
- 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
- 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
- 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
- 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
- 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
- 'TCCR2B_FOC2A': '$80', # Force Output Compare A
- 'TCCR2B_FOC2B': '$40', # Force Output Compare B
- 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
- 'TCCR2B_CS2': '$7', # Clock Select bits
- 'TCNT2' : '$b2', # Timer/Counter2
- 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
- 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
- 'ASSR' : '$b6', # Asynchronous Status Register
- 'ASSR_EXCLK': '$40', # Enable External Clock Input
- 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
- 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
- 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
- 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
- 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
- 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
- 'GTCCR' : '$43', # General Timer Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
-
-# Module AD_CONVERTER
- 'ADMUX' : '$7c', # The ADC multiplexer Selection
- 'ADMUX_REFS': '$c0', # Reference Selection Bits
- 'ADMUX_ADLAR': '$20', # Left Adjust Result
- 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
- 'ADC' : '$78', # ADC Data Register Bytes
- 'ADCSRA' : '$7a', # The ADC Control and Status reg
- 'ADCSRA_ADEN': '$80', # ADC Enable
- 'ADCSRA_ADSC': '$40', # ADC Start Conversion
- 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
- 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
- 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
- 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
- 'ADCSRB' : '$7b', # The ADC Control and Status reg
- 'ADCSRB_ACME': '$40', #
- 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
- 'DIDR0' : '$7e', # Digital Input Disable Register
- 'DIDR0_ADC5D': '$20', #
- 'DIDR0_ADC4D': '$10', #
- 'DIDR0_ADC3D': '$8', #
- 'DIDR0_ADC2D': '$4', #
- 'DIDR0_ADC1D': '$2', #
- 'DIDR0_ADC0D': '$1', #
-
-# Module ANALOG_COMPARATOR
- 'ACSR' : '$50', # Analog Comparator Control And
- 'ACSR_ACD': '$80', # Analog Comparator Disable
- 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
- 'ACSR_ACO': '$20', # Analog Compare Output
- 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
- 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
- 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
- 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
- 'DIDR1' : '$7f', # Digital Input Disable Register
- 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
- 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
-
-# Module PORTB
- 'PORTB' : '$25', # Port B Data Register
- 'DDRB' : '$24', # Port B Data Direction Register
- 'PINB' : '$23', # Port B Input Pins
-
-# Module PORTC
- 'PORTC' : '$28', # Port C Data Register
- 'DDRC' : '$27', # Port C Data Direction Register
- 'PINC' : '$26', # Port C Input Pins
-
-# Module PORTD
- 'PORTD' : '$2b', # Port D Data Register
- 'DDRD' : '$2a', # Port D Data Direction Register
- 'PIND' : '$29', # Port D Input Pins
-
-# Module TIMER_COUNTER_0
- 'OCR0B' : '$48', # Timer/Counter0 Output Compare
- 'OCR0A' : '$47', # Timer/Counter0 Output Compare
- 'TCNT0' : '$46', # Timer/Counter0
- 'TCCR0B' : '$45', # Timer/Counter Control Register
- 'TCCR0B_FOC0A': '$80', # Force Output Compare A
- 'TCCR0B_FOC0B': '$40', # Force Output Compare B
- 'TCCR0B_WGM02': '$8', #
- 'TCCR0B_CS0': '$7', # Clock Select
- 'TCCR0A' : '$44', # Timer/Counter Control Registe
- 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
- 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
- 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
- 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
- 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
- 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
- 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
- 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
- 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
- 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
- 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
- 'GTCCR' : '$43', # General Timer/Counter Control
- 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
- 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
-
-# Module EXTERNAL_INTERRUPT
- 'EICRA' : '$69', # External Interrupt Control Reg
- 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
- 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
- 'EIMSK' : '$3d', # External Interrupt Mask Regist
- 'EIMSK_INT': '$3', # External Interrupt Request 1 E
- 'EIFR' : '$3c', # External Interrupt Flag Regist
- 'EIFR_INTF': '$3', # External Interrupt Flags
- 'PCICR' : '$68', # Pin Change Interrupt Control R
- 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
- 'PCMSK2' : '$6d', # Pin Change Mask Register 2
- 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
- 'PCMSK1' : '$6c', # Pin Change Mask Register 1
- 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
- 'PCMSK0' : '$6b', # Pin Change Mask Register 0
- 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
- 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
- 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
-
-# Module SPI
- 'SPDR' : '$4e', # SPI Data Register
- 'SPSR' : '$4d', # SPI Status Register
- 'SPSR_SPIF': '$80', # SPI Interrupt Flag
- 'SPSR_WCOL': '$40', # Write Collision Flag
- 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
- 'SPCR' : '$4c', # SPI Control Register
- 'SPCR_SPIE': '$80', # SPI Interrupt Enable
- 'SPCR_SPE': '$40', # SPI Enable
- 'SPCR_DORD': '$20', # Data Order
- 'SPCR_MSTR': '$10', # Master/Slave Select
- 'SPCR_CPOL': '$8', # Clock polarity
- 'SPCR_CPHA': '$4', # Clock Phase
- 'SPCR_SPR': '$3', # SPI Clock Rate Selects
-
-# Module CPU
- 'PRR' : '$64', # Power Reduction Register
- 'PRR_PRTWI': '$80', # Power Reduction TWI
- 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
- 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
- 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
- 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
- 'PRR_PRUSART0': '$2', # Power Reduction USART
- 'PRR_PRADC': '$1', # Power Reduction ADC
- 'OSCCAL' : '$66', # Oscillator Calibration Value
- 'CLKPR' : '$61', # Clock Prescale Register
- 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
- 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
- 'SREG' : '$5f', # Status Register
- 'SREG_I': '$80', # Global Interrupt Enable
- 'SREG_T': '$40', # Bit Copy Storage
- 'SREG_H': '$20', # Half Carry Flag
- 'SREG_S': '$10', # Sign Bit
- 'SREG_V': '$8', # Two's Complement Overflow Flag
- 'SREG_N': '$4', # Negative Flag
- 'SREG_Z': '$2', # Zero Flag
- 'SREG_C': '$1', # Carry Flag
- 'SP' : '$5d', # Stack Pointer
- 'SPMCSR' : '$57', # Store Program Memory Control a
- 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
- 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
- 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
- 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
- 'SPMCSR_PGWRT': '$4', # Page Write
- 'SPMCSR_PGERS': '$2', # Page Erase
- 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
- 'MCUCR' : '$55', # MCU Control Register
- 'MCUCR_PUD': '$10', #
- 'MCUCR_IVSEL': '$2', #
- 'MCUCR_IVCE': '$1', #
- 'MCUSR' : '$54', # MCU Status Register
- 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
- 'MCUSR_BORF': '$4', # Brown-out Reset Flag
- 'MCUSR_EXTRF': '$2', # External Reset Flag
- 'MCUSR_PORF': '$1', # Power-on reset flag
- 'SMCR' : '$53', #
- 'SMCR_SM': '$e', #
- 'SMCR_SE': '$1', #
- 'GPIOR2' : '$4b', # General Purpose I/O Register 2
- 'GPIOR1' : '$4a', # General Purpose I/O Register 1
- 'GPIOR0' : '$3e', # General Purpose I/O Register 0
-
-# Module WATCHDOG
- 'WDTCSR' : '$60', # Watchdog Timer Control Registe
- 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
- 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
- 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
- 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
- 'WDTCSR_WDE': '$8', # Watch Dog Enable
-
-# Module EEPROM
- 'EEAR' : '$41', # EEPROM Address Register Bytes
- 'EEDR' : '$40', # EEPROM Data Register
- 'EECR' : '$3f', # EEPROM Control Register
- 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
- 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
- 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
- 'EECR_EEPE': '$2', # EEPROM Write Enable
- 'EECR_EERE': '$1', # EEPROM Read Enable
-
- '__amforth_dummy':'0'
-}
diff --git a/amforth-6.5/avr8/devices/atmega168/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega168/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega168/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega168/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega168/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168/words/sleep.asm b/amforth-6.5/avr8/devices/atmega168/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega168/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT