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-rw-r--r--amforth-6.5/avr8/devices/atmega8/atmega8.frt207
-rw-r--r--amforth-6.5/avr8/devices/atmega8/device.asm95
-rw-r--r--amforth-6.5/avr8/devices/atmega8/device.inc696
-rw-r--r--amforth-6.5/avr8/devices/atmega8/device.py191
-rw-r--r--amforth-6.5/avr8/devices/atmega8/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega8/words/no-wdt.asm22
-rw-r--r--amforth-6.5/avr8/devices/atmega8/words/sleep.asm24
7 files changed, 0 insertions, 1249 deletions
diff --git a/amforth-6.5/avr8/devices/atmega8/atmega8.frt b/amforth-6.5/avr8/devices/atmega8/atmega8.frt
deleted file mode 100644
index 0149247..0000000
--- a/amforth-6.5/avr8/devices/atmega8/atmega8.frt
+++ /dev/null
@@ -1,207 +0,0 @@
-\ Partname: ATmega8
-\ generated automatically
-
-\ ANALOG_COMPARATOR
-&80 constant SFIOR \ Special Function IO Register
- $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
-&40 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-\ SPI
-&47 constant SPDR \ SPI Data Register
-&46 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&45 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-\ EXTERNAL_INTERRUPT
-&91 constant GICR \ General Interrupt Control Register
- $C0 constant GICR_INT \ External Interrupt Request 1 Enable
- $02 constant GICR_IVSEL \ Interrupt Vector Select
- $01 constant GICR_IVCE \ Interrupt Vector Change Enable
-&90 constant GIFR \ General Interrupt Flag Register
- $C0 constant GIFR_INTF \ External Interrupt Flags
-&85 constant MCUCR \ MCU Control Register
- $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
- $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
-\ TIMER_COUNTER_0
-&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
- $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&88 constant TIFR \ Timer/Counter Interrupt Flag register
- $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
-&83 constant TCCR0 \ Timer/Counter0 Control Register
- $04 constant TCCR0_CS02 \ Clock Select0 bit 2
- $02 constant TCCR0_CS01 \ Clock Select0 bit 1
- $01 constant TCCR0_CS00 \ Clock Select0 bit 0
-&82 constant TCNT0 \ Timer Counter 0
-\ TIMER_COUNTER_1
-&79 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
- $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&78 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&76 constant TCNT1 \ Timer/Counter1 Bytes
-&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
-&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
-&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-\ TIMER_COUNTER_2
-&69 constant TCCR2 \ Timer/Counter2 Control Register
- $80 constant TCCR2_FOC2 \ Force Output Compare
- $40 constant TCCR2_WGM20 \ Waveform Genration Mode
- $30 constant TCCR2_COM2 \ Compare Output Mode bits
- $08 constant TCCR2_WGM21 \ Waveform Generation Mode
- $07 constant TCCR2_CS2 \ Clock Select bits
-&68 constant TCNT2 \ Timer/Counter2
-&67 constant OCR2 \ Timer/Counter2 Output Compare Register
-&66 constant ASSR \ Asynchronous Status Register
- $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
- $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
- $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
- $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
-\ USART
-&44 constant UDR \ USART I/O Data Register
-&43 constant UCSRA \ USART Control and Status Register A
- $80 constant UCSRA_RXC \ USART Receive Complete
- $40 constant UCSRA_TXC \ USART Transmitt Complete
- $20 constant UCSRA_UDRE \ USART Data Register Empty
- $10 constant UCSRA_FE \ Framing Error
- $08 constant UCSRA_DOR \ Data overRun
- $04 constant UCSRA_UPE \ Parity Error
- $02 constant UCSRA_U2X \ Double the USART transmission speed
- $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
-&42 constant UCSRB \ USART Control and Status Register B
- $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
- $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
- $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
- $10 constant UCSRB_RXEN \ Receiver Enable
- $08 constant UCSRB_TXEN \ Transmitter Enable
- $04 constant UCSRB_UCSZ2 \ Character Size
- $02 constant UCSRB_RXB8 \ Receive Data Bit 8
- $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
-&64 constant UCSRC \ USART Control and Status Register C
- $80 constant UCSRC_URSEL \ Register Select
- $40 constant UCSRC_UMSEL \ USART Mode Select
- $30 constant UCSRC_UPM \ Parity Mode Bits
- $08 constant UCSRC_USBS \ Stop Bit Select
- $06 constant UCSRC_UCSZ \ Character Size
- $01 constant UCSRC_UCPOL \ Clock Polarity
-&64 constant UBRRH \ USART Baud Rate Register Hight Byte
-&41 constant UBRRL \ USART Baud Rate Register Low Byte
-\ TWI
-&32 constant TWBR \ TWI Bit Rate register
-&86 constant TWCR \ TWI Control Register
- $80 constant TWCR_TWINT \ TWI Interrupt Flag
- $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
- $20 constant TWCR_TWSTA \ TWI Start Condition Bit
- $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
- $08 constant TWCR_TWWC \ TWI Write Collition Flag
- $04 constant TWCR_TWEN \ TWI Enable Bit
- $01 constant TWCR_TWIE \ TWI Interrupt Enable
-&33 constant TWSR \ TWI Status Register
- $F8 constant TWSR_TWS \ TWI Status
- $03 constant TWSR_TWPS \ TWI Prescaler
-&35 constant TWDR \ TWI Data register
-&34 constant TWAR \ TWI (Slave) Address register
- $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
- $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
-\ WATCHDOG
-&65 constant WDTCR \ Watchdog Timer Control Register
- $10 constant WDTCR_WDCE \ Watchdog Change Enable
- $08 constant WDTCR_WDE \ Watch Dog Enable
- $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
-\ PORTB
-&56 constant PORTB \ Port B Data Register
-&55 constant DDRB \ Port B Data Direction Register
-&54 constant PINB \ Port B Input Pins
-\ PORTC
-&53 constant PORTC \ Port C Data Register
-&52 constant DDRC \ Port C Data Direction Register
-&51 constant PINC \ Port C Input Pins
-\ PORTD
-&50 constant PORTD \ Port D Data Register
-&49 constant DDRD \ Port D Data Direction Register
-&48 constant PIND \ Port D Input Pins
-\ EEPROM
-&62 constant EEAR \ EEPROM Address Register Bytes
-&61 constant EEDR \ EEPROM Data Register
-&60 constant EECR \ EEPROM Control Register
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMWE \ EEPROM Master Write Enable
- $02 constant EECR_EEWE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&84 constant MCUCSR \ MCU Control And Status Register
- $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUCSR_BORF \ Brown-out Reset Flag
- $02 constant MCUCSR_EXTRF \ External Reset Flag
- $01 constant MCUCSR_PORF \ Power-on reset flag
-&81 constant OSCCAL \ Oscillator Calibration Value
-&87 constant SPMCR \ Store Program Memory Control Register
- $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCR_RWWSB \ Read-While-Write Section Busy
- $10 constant SPMCR_RWWSRE \ Read-While-Write Section Read Enable
- $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCR_PGWRT \ Page Write
- $02 constant SPMCR_PGERS \ Page Erase
- $01 constant SPMCR_SPMEN \ Store Program Memory Enable
-\ AD_CONVERTER
-&39 constant ADMUX \ The ADC multiplexer Selection Register
- $C0 constant ADMUX_REFS \ Reference Selection Bits
- $20 constant ADMUX_ADLAR \ Left Adjust Result
- $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
-&38 constant ADCSRA \ The ADC Control and Status register
- $80 constant ADCSRA_ADEN \ ADC Enable
- $40 constant ADCSRA_ADSC \ ADC Start Conversion
- $20 constant ADCSRA_ADFR \ ADC Free Running Select
- $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
- $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
- $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
-&36 constant ADC \ ADC Data Register Bytes
-
-\ Interrupts
-&1 constant INT0Addr \ External Interrupt Request 0
-&2 constant INT1Addr \ External Interrupt Request 1
-&3 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-&4 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-&5 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-&6 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-&7 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-&8 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&9 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&10 constant SPI__STCAddr \ Serial Transfer Complete
-&11 constant USART__RXCAddr \ USART, Rx Complete
-&12 constant USART__UDREAddr \ USART Data Register Empty
-&13 constant USART__TXCAddr \ USART, Tx Complete
-&14 constant ADCAddr \ ADC Conversion Complete
-&15 constant EE_RDYAddr \ EEPROM Ready
-&16 constant ANA_COMPAddr \ Analog Comparator
-&17 constant TWIAddr \ 2-wire Serial Interface
-&18 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega8/device.asm b/amforth-6.5/avr8/devices/atmega8/device.asm
deleted file mode 100644
index d822d36..0000000
--- a/amforth-6.5/avr8/devices/atmega8/device.asm
+++ /dev/null
@@ -1,95 +0,0 @@
-; Partname: ATmega8
-; generated automatically, do not edit
-
-.nolist
- .include "m8def.inc"
-.list
-
-.equ ramstart = 96
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_SPI = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_USART = 0
-.set WANT_TWI = 0
-.set WANT_WATCHDOG = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_EEPROM = 0
-.set WANT_CPU = 0
-.set WANT_AD_CONVERTER = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 1
- rcall isr ; External Interrupt Request 0
-.org 2
- rcall isr ; External Interrupt Request 1
-.org 3
- rcall isr ; Timer/Counter2 Compare Match
-.org 4
- rcall isr ; Timer/Counter2 Overflow
-.org 5
- rcall isr ; Timer/Counter1 Capture Event
-.org 6
- rcall isr ; Timer/Counter1 Compare Match A
-.org 7
- rcall isr ; Timer/Counter1 Compare Match B
-.org 8
- rcall isr ; Timer/Counter1 Overflow
-.org 9
- rcall isr ; Timer/Counter0 Overflow
-.org 10
- rcall isr ; Serial Transfer Complete
-.org 11
- rcall isr ; USART, Rx Complete
-.org 12
- rcall isr ; USART Data Register Empty
-.org 13
- rcall isr ; USART, Tx Complete
-.org 14
- rcall isr ; ADC Conversion Complete
-.org 15
- rcall isr ; EEPROM Ready
-.org 16
- rcall isr ; Analog Comparator
-.org 17
- rcall isr ; 2-wire Serial Interface
-.org 18
- rcall isr ; Store Program Memory Ready
-.equ INTVECTORS = 19
-.nooverlap
-
-; compatability layer (maybe empty)
-.equ SPMCSR = SPMCR
-.equ EEPE = EEWE
-.equ EEMPE = EEMWE
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 1024
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 6144
-mcu_numints:
- .dw 19
-mcu_name:
- .dw 7
- .db "ATmega8",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8/device.inc b/amforth-6.5/avr8/devices/atmega8/device.inc
deleted file mode 100644
index 733b5ed..0000000
--- a/amforth-6.5/avr8/devices/atmega8/device.inc
+++ /dev/null
@@ -1,696 +0,0 @@
-; Partname: ATmega8
-; generated automatically, no not edit
-
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Special Function IO Register
-VE_SFIOR:
- .dw $ff05
- .db "SFIOR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SFIOR
-XT_SFIOR:
- .dw PFA_DOVARIABLE
-PFA_SFIOR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 40
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 47
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 46
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 45
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Control Register
-VE_GICR:
- .dw $ff04
- .db "GICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GICR
-XT_GICR:
- .dw PFA_DOVARIABLE
-PFA_GICR:
- .dw 91
-; ( -- addr ) System Constant
-; R( -- )
-; General Interrupt Flag Register
-VE_GIFR:
- .dw $ff04
- .db "GIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_GIFR
-XT_GIFR:
- .dw PFA_DOVARIABLE
-PFA_GIFR:
- .dw 90
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw 89
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw 88
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Timer Counter 0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 82
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 79
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 78
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 70
-
-.endif
-.if WANT_TIMER_COUNTER_2 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw 67
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronous Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw 66
-
-.endif
-.if WANT_USART == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw 44
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSRA:
- .dw $ff05
- .db "UCSRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRA
-XT_UCSRA:
- .dw PFA_DOVARIABLE
-PFA_UCSRA:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSRB:
- .dw $ff05
- .db "UCSRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRB
-XT_UCSRB:
- .dw PFA_DOVARIABLE
-PFA_UCSRB:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSRC:
- .dw $ff05
- .db "UCSRC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSRC
-XT_UCSRC:
- .dw PFA_DOVARIABLE
-PFA_UCSRC:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Hight Byte
-VE_UBRRH:
- .dw $ff05
- .db "UBRRH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRH
-XT_UBRRH:
- .dw PFA_DOVARIABLE
-PFA_UBRRH:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Low Byte
-VE_UBRRL:
- .dw $ff05
- .db "UBRRL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRRL
-XT_UBRRL:
- .dw PFA_DOVARIABLE
-PFA_UBRRL:
- .dw 41
-
-.endif
-.if WANT_TWI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Bit Rate register
-VE_TWBR:
- .dw $ff04
- .db "TWBR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWBR
-XT_TWBR:
- .dw PFA_DOVARIABLE
-PFA_TWBR:
- .dw 32
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Control Register
-VE_TWCR:
- .dw $ff04
- .db "TWCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWCR
-XT_TWCR:
- .dw PFA_DOVARIABLE
-PFA_TWCR:
- .dw 86
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Status Register
-VE_TWSR:
- .dw $ff04
- .db "TWSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWSR
-XT_TWSR:
- .dw PFA_DOVARIABLE
-PFA_TWSR:
- .dw 33
-; ( -- addr ) System Constant
-; R( -- )
-; TWI Data register
-VE_TWDR:
- .dw $ff04
- .db "TWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWDR
-XT_TWDR:
- .dw PFA_DOVARIABLE
-PFA_TWDR:
- .dw 35
-; ( -- addr ) System Constant
-; R( -- )
-; TWI (Slave) Address register
-VE_TWAR:
- .dw $ff04
- .db "TWAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TWAR
-XT_TWAR:
- .dw PFA_DOVARIABLE
-PFA_TWAR:
- .dw 34
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw 65
-
-.endif
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 56
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 55
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 54
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 52
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 51
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 50
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 49
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 48
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 60
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control And Status Register
-VE_MCUCSR:
- .dw $ff06
- .db "MCUCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCSR
-XT_MCUCSR:
- .dw PFA_DOVARIABLE
-PFA_MCUCSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 81
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCR:
- .dw $ff05
- .db "SPMCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCR
-XT_SPMCR:
- .dw PFA_DOVARIABLE
-PFA_SPMCR:
- .dw 87
-
-.endif
-.if WANT_AD_CONVERTER == 1
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSRA:
- .dw $ff06
- .db "ADCSRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSRA
-XT_ADCSRA:
- .dw PFA_DOVARIABLE
-PFA_ADCSRA:
- .dw 38
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Bytes
-VE_ADC:
- .dw $ff03
- .db "ADC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADC
-XT_ADC:
- .dw PFA_DOVARIABLE
-PFA_ADC:
- .dw 36
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega8/device.py b/amforth-6.5/avr8/devices/atmega8/device.py
deleted file mode 100644
index 9f561f5..0000000
--- a/amforth-6.5/avr8/devices/atmega8/device.py
+++ /dev/null
@@ -1,191 +0,0 @@
-# Partname: ATmega8
-# generated automatically, do not edit
-MCUREGS = {
- 'SFIOR': '&80',
- 'SFIOR_ACME': '$08',
- 'ACSR': '&40',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'SPDR': '&47',
- 'SPSR': '&46',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPCR': '&45',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'GICR': '&91',
- 'GICR_INT': '$C0',
- 'GICR_IVSEL': '$02',
- 'GICR_IVCE': '$01',
- 'GIFR': '&90',
- 'GIFR_INTF': '$C0',
- 'MCUCR': '&85',
- 'MCUCR_ISC1': '$0C',
- 'MCUCR_ISC0': '$03',
- 'TIMSK': '&89',
- 'TIMSK_TOIE0': '$01',
- 'TIFR': '&88',
- 'TIFR_TOV0': '$01',
- 'TCCR0': '&83',
- 'TCCR0_CS02': '$04',
- 'TCCR0_CS01': '$02',
- 'TCCR0_CS00': '$01',
- 'TCNT0': '&82',
- 'TCCR1A': '&79',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_FOC1A': '$08',
- 'TCCR1A_FOC1B': '$04',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&78',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCNT1': '&76',
- 'OCR1A': '&74',
- 'OCR1B': '&72',
- 'ICR1': '&70',
- 'TCCR2': '&69',
- 'TCCR2_FOC2': '$80',
- 'TCCR2_WGM20': '$40',
- 'TCCR2_COM2': '$30',
- 'TCCR2_WGM21': '$08',
- 'TCCR2_CS2': '$07',
- 'TCNT2': '&68',
- 'OCR2': '&67',
- 'ASSR': '&66',
- 'ASSR_AS2': '$08',
- 'ASSR_TCN2UB': '$04',
- 'ASSR_OCR2UB': '$02',
- 'ASSR_TCR2UB': '$01',
- 'UDR': '&44',
- 'UCSRA': '&43',
- 'UCSRA_RXC': '$80',
- 'UCSRA_TXC': '$40',
- 'UCSRA_UDRE': '$20',
- 'UCSRA_FE': '$10',
- 'UCSRA_DOR': '$08',
- 'UCSRA_UPE': '$04',
- 'UCSRA_U2X': '$02',
- 'UCSRA_MPCM': '$01',
- 'UCSRB': '&42',
- 'UCSRB_RXCIE': '$80',
- 'UCSRB_TXCIE': '$40',
- 'UCSRB_UDRIE': '$20',
- 'UCSRB_RXEN': '$10',
- 'UCSRB_TXEN': '$08',
- 'UCSRB_UCSZ2': '$04',
- 'UCSRB_RXB8': '$02',
- 'UCSRB_TXB8': '$01',
- 'UCSRC': '&64',
- 'UCSRC_URSEL': '$80',
- 'UCSRC_UMSEL': '$40',
- 'UCSRC_UPM': '$30',
- 'UCSRC_USBS': '$08',
- 'UCSRC_UCSZ': '$06',
- 'UCSRC_UCPOL': '$01',
- 'UBRRH': '&64',
- 'UBRRL': '&41',
- 'TWBR': '&32',
- 'TWCR': '&86',
- 'TWCR_TWINT': '$80',
- 'TWCR_TWEA': '$40',
- 'TWCR_TWSTA': '$20',
- 'TWCR_TWSTO': '$10',
- 'TWCR_TWWC': '$08',
- 'TWCR_TWEN': '$04',
- 'TWCR_TWIE': '$01',
- 'TWSR': '&33',
- 'TWSR_TWS': '$F8',
- 'TWSR_TWPS': '$03',
- 'TWDR': '&35',
- 'TWAR': '&34',
- 'TWAR_TWA': '$FE',
- 'TWAR_TWGCE': '$01',
- 'WDTCR': '&65',
- 'WDTCR_WDCE': '$10',
- 'WDTCR_WDE': '$08',
- 'WDTCR_WDP': '$07',
- 'PORTB': '&56',
- 'DDRB': '&55',
- 'PINB': '&54',
- 'PORTC': '&53',
- 'DDRC': '&52',
- 'PINC': '&51',
- 'PORTD': '&50',
- 'DDRD': '&49',
- 'PIND': '&48',
- 'EEAR': '&62',
- 'EEDR': '&61',
- 'EECR': '&60',
- 'EECR_EERIE': '$08',
- 'EECR_EEMWE': '$04',
- 'EECR_EEWE': '$02',
- 'EECR_EERE': '$01',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'MCUCSR': '&84',
- 'MCUCSR_WDRF': '$08',
- 'MCUCSR_BORF': '$04',
- 'MCUCSR_EXTRF': '$02',
- 'MCUCSR_PORF': '$01',
- 'OSCCAL': '&81',
- 'SPMCR': '&87',
- 'SPMCR_SPMIE': '$80',
- 'SPMCR_RWWSB': '$40',
- 'SPMCR_RWWSRE': '$10',
- 'SPMCR_BLBSET': '$08',
- 'SPMCR_PGWRT': '$04',
- 'SPMCR_PGERS': '$02',
- 'SPMCR_SPMEN': '$01',
- 'ADMUX': '&39',
- 'ADMUX_REFS': '$C0',
- 'ADMUX_ADLAR': '$20',
- 'ADMUX_MUX': '$0F',
- 'ADCSRA': '&38',
- 'ADCSRA_ADEN': '$80',
- 'ADCSRA_ADSC': '$40',
- 'ADCSRA_ADFR': '$20',
- 'ADCSRA_ADIF': '$10',
- 'ADCSRA_ADIE': '$08',
- 'ADCSRA_ADPS': '$07',
- 'ADC': '&36',
- 'INT0Addr': '1',
- 'INT1Addr': '2',
- 'TIMER2_COMPAddr': '3',
- 'TIMER2_OVFAddr': '4',
- 'TIMER1_CAPTAddr': '5',
- 'TIMER1_COMPAAddr': '6',
- 'TIMER1_COMPBAddr': '7',
- 'TIMER1_OVFAddr': '8',
- 'TIMER0_OVFAddr': '9',
- 'SPI__STCAddr': '10',
- 'USART__RXCAddr': '11',
- 'USART__UDREAddr': '12',
- 'USART__TXCAddr': '13',
- 'ADCAddr': '14',
- 'EE_RDYAddr': '15',
- 'ANA_COMPAddr': '16',
- 'TWIAddr': '17',
- 'SPM_RDYAddr': '18'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega8/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8/words/no-wdt.asm
deleted file mode 100644
index 4a12261..0000000
--- a/amforth-6.5/avr8/devices/atmega8/words/no-wdt.asm
+++ /dev/null
@@ -1,22 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
-; Reset WDT
- wdr
-; Write logical one to WDTOE and WDE
- in_ temp1, WDTCR
- ori temp1, (1<<WDTOE)|(1<<WDE)
- out WDTCR, temp1
-; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCR, temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8/words/sleep.asm
deleted file mode 100644
index 778fa32..0000000
--- a/amforth-6.5/avr8/devices/atmega8/words/sleep.asm
+++ /dev/null
@@ -1,24 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- swap tosl ; move to correct location (bits 6-4, atmega32)
- ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
- out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
- sleep ; nighty-night
-;; the 4 lower bits of MCUCR should not be touched
- in_ tosl, MCUCR
- andi tosl, $0F
- out_ MCUCR, tosl
- ;clr tosl ; need to clean up the SMCR reg before we leave
- ;out SMCR, tosl ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp DO_NEXT