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-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/atmega8u2.frt357
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/device.asm112
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/device.inc1128
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/device.py341
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/words/sleep.asm19
7 files changed, 0 insertions, 2005 deletions
diff --git a/amforth-6.5/avr8/devices/atmega8u2/atmega8u2.frt b/amforth-6.5/avr8/devices/atmega8u2/atmega8u2.frt
deleted file mode 100644
index 5c42559..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/atmega8u2.frt
+++ /dev/null
@@ -1,357 +0,0 @@
-\ Partname: ATmega8U2
-\ generated automatically
-
-\ PORTB
-&37 constant PORTB \ Port B Data Register
-&36 constant DDRB \ Port B Data Direction Register
-&35 constant PINB \ Port B Input Pins
-\ PORTD
-&43 constant PORTD \ Port D Data Register
-&42 constant DDRD \ Port D Data Direction Register
-&41 constant PIND \ Port D Input Pins
-\ SPI
-&76 constant SPCR \ SPI Control Register
- $80 constant SPCR_SPIE \ SPI Interrupt Enable
- $40 constant SPCR_SPE \ SPI Enable
- $20 constant SPCR_DORD \ Data Order
- $10 constant SPCR_MSTR \ Master/Slave Select
- $08 constant SPCR_CPOL \ Clock polarity
- $04 constant SPCR_CPHA \ Clock Phase
- $03 constant SPCR_SPR \ SPI Clock Rate Selects
-&77 constant SPSR \ SPI Status Register
- $80 constant SPSR_SPIF \ SPI Interrupt Flag
- $40 constant SPSR_WCOL \ Write Collision Flag
- $01 constant SPSR_SPI2X \ Double SPI Speed Bit
-&78 constant SPDR \ SPI Data Register
-\ BOOT_LOAD
-&87 constant SPMCSR \ Store Program Memory Control Register
- $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
- $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
- $20 constant SPMCSR_SIGRD \ Signature Row Read
- $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
- $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
- $04 constant SPMCSR_PGWRT \ Page Write
- $02 constant SPMCSR_PGERS \ Page Erase
- $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
-\ EEPROM
-&65 constant EEAR \ EEPROM Address Register Low Bytes
-&64 constant EEDR \ EEPROM Data Register
-&63 constant EECR \ EEPROM Control Register
- $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
- $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
- $04 constant EECR_EEMPE \ EEPROM Master Write Enable
- $02 constant EECR_EEPE \ EEPROM Write Enable
- $01 constant EECR_EERE \ EEPROM Read Enable
-\ TIMER_COUNTER_0
-&72 constant OCR0B \ Timer/Counter0 Output Compare Register
-&71 constant OCR0A \ Timer/Counter0 Output Compare Register
-&70 constant TCNT0 \ Timer/Counter0
-&69 constant TCCR0B \ Timer/Counter Control Register B
- $80 constant TCCR0B_FOC0A \ Force Output Compare A
- $40 constant TCCR0B_FOC0B \ Force Output Compare B
- $08 constant TCCR0B_WGM02 \
- $07 constant TCCR0B_CS0 \ Clock Select
-&68 constant TCCR0A \ Timer/Counter Control Register A
- $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
- $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
- $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
-&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
- $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
- $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
- $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
-&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
- $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
- $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
- $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
-&67 constant GTCCR \ General Timer/Counter Control Register
- $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
- $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
-\ TIMER_COUNTER_1
-&128 constant TCCR1A \ Timer/Counter1 Control Register A
- $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
- $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
- $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
- $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
-&129 constant TCCR1B \ Timer/Counter1 Control Register B
- $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
- $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
- $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
- $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
-&130 constant TCCR1C \ Timer/Counter 1 Control Register C
- $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
- $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
- $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
-&132 constant TCNT1 \ Timer/Counter1 Bytes
-&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
-&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
-&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
-&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
-&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
- $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
- $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
- $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
- $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
- $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
-&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
- $20 constant TIFR1_ICF1 \ Input Capture Flag 1
- $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
- $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
- $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
- $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
-\ PLL
-&73 constant PLLCSR \ PLL Status and Control register
- $1C constant PLLCSR_PLLP \ PLL prescaler Bits
- $02 constant PLLCSR_PLLE \ PLL Enable Bit
- $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
-\ USB_DEVICE
-&244 constant UEINT \
-&242 constant UEBCLX \
-&241 constant UEDATX \
-&240 constant UEIENX \
- $80 constant UEIENX_FLERRE \
- $40 constant UEIENX_NAKINE \
- $10 constant UEIENX_NAKOUTE \
- $08 constant UEIENX_RXSTPE \
- $04 constant UEIENX_RXOUTE \
- $02 constant UEIENX_STALLEDE \
- $01 constant UEIENX_TXINE \
-&239 constant UESTA1X \
- $04 constant UESTA1X_CTRLDIR \
- $03 constant UESTA1X_CURRBK \
-&238 constant UESTA0X \
- $80 constant UESTA0X_CFGOK \
- $40 constant UESTA0X_OVERFI \
- $20 constant UESTA0X_UNDERFI \
- $0C constant UESTA0X_DTSEQ \
- $03 constant UESTA0X_NBUSYBK \
-&237 constant UECFG1X \
- $70 constant UECFG1X_EPSIZE \
- $0C constant UECFG1X_EPBK \
- $02 constant UECFG1X_ALLOC \
-&236 constant UECFG0X \
- $C0 constant UECFG0X_EPTYPE \
- $01 constant UECFG0X_EPDIR \
-&235 constant UECONX \
- $20 constant UECONX_STALLRQ \
- $10 constant UECONX_STALLRQC \
- $08 constant UECONX_RSTDT \
- $01 constant UECONX_EPEN \
-&234 constant UERST \
- $1F constant UERST_EPRST \
-&233 constant UENUM \
-&232 constant UEINTX \
- $80 constant UEINTX_FIFOCON \
- $40 constant UEINTX_NAKINI \
- $20 constant UEINTX_RWAL \
- $10 constant UEINTX_NAKOUTI \
- $08 constant UEINTX_RXSTPI \
- $04 constant UEINTX_RXOUTI \
- $02 constant UEINTX_STALLEDI \
- $01 constant UEINTX_TXINI \
-&230 constant UDMFN \
- $10 constant UDMFN_FNCERR \
-&228 constant UDFNUM \
-&227 constant UDADDR \
- $80 constant UDADDR_ADDEN \
- $7F constant UDADDR_UADD \
-&226 constant UDIEN \
- $40 constant UDIEN_UPRSME \
- $20 constant UDIEN_EORSME \
- $10 constant UDIEN_WAKEUPE \
- $08 constant UDIEN_EORSTE \
- $04 constant UDIEN_SOFE \
- $01 constant UDIEN_SUSPE \
-&225 constant UDINT \
- $40 constant UDINT_UPRSMI \
- $20 constant UDINT_EORSMI \
- $10 constant UDINT_WAKEUPI \
- $08 constant UDINT_EORSTI \
- $04 constant UDINT_SOFI \
- $01 constant UDINT_SUSPI \
-&224 constant UDCON \
- $04 constant UDCON_RSTCPU \
- $02 constant UDCON_RMWKUP \
- $01 constant UDCON_DETACH \
-&216 constant USBCON \ USB General Control Register
- $80 constant USBCON_USBE \
- $20 constant USBCON_FRZCLK \
-&99 constant REGCR \ Regulator Control Register
- $01 constant REGCR_REGDIS \
-\ CPU
-&95 constant SREG \ Status Register
- $80 constant SREG_I \ Global Interrupt Enable
- $40 constant SREG_T \ Bit Copy Storage
- $20 constant SREG_H \ Half Carry Flag
- $10 constant SREG_S \ Sign Bit
- $08 constant SREG_V \ Two's Complement Overflow Flag
- $04 constant SREG_N \ Negative Flag
- $02 constant SREG_Z \ Zero Flag
- $01 constant SREG_C \ Carry Flag
-&93 constant SP \ Stack Pointer
-&85 constant MCUCR \ MCU Control Register
- $10 constant MCUCR_PUD \ Pull-up disable
- $02 constant MCUCR_IVSEL \ Interrupt Vector Select
- $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
-&84 constant MCUSR \ MCU Status Register
- $20 constant MCUSR_USBRF \ USB reset flag
- $08 constant MCUSR_WDRF \ Watchdog Reset Flag
- $04 constant MCUSR_BORF \ Brown-out Reset Flag
- $02 constant MCUSR_EXTRF \ External Reset Flag
- $01 constant MCUSR_PORF \ Power-on reset flag
-&102 constant OSCCAL \ Oscillator Calibration Value
-&97 constant CLKPR \
- $80 constant CLKPR_CLKPCE \
- $0F constant CLKPR_CLKPS \
-&83 constant SMCR \ Sleep Mode Control Register
- $0E constant SMCR_SM \ Sleep Mode Select bits
- $01 constant SMCR_SE \ Sleep Enable
-&92 constant EIND \ Extended Indirect Register
-&75 constant GPIOR2 \ General Purpose IO Register 2
- $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
-&74 constant GPIOR1 \ General Purpose IO Register 1
- $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
-&62 constant GPIOR0 \ General Purpose IO Register 0
- $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
- $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
- $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
- $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
- $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
- $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
- $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
- $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
-&101 constant PRR1 \ Power Reduction Register1
- $80 constant PRR1_PRUSB \ Power Reduction USB
- $01 constant PRR1_PRUSART1 \ Power Reduction USART1
-&100 constant PRR0 \ Power Reduction Register0
- $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
- $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
- $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
-&210 constant CLKSTA \
- $02 constant CLKSTA_RCON \
- $01 constant CLKSTA_EXTON \
-&209 constant CLKSEL1 \
- $F0 constant CLKSEL1_RCCKSEL \
- $0F constant CLKSEL1_EXCKSEL \
-&208 constant CLKSEL0 \
- $C0 constant CLKSEL0_RCSUT \
- $30 constant CLKSEL0_EXSUT \
- $08 constant CLKSEL0_RCE \
- $04 constant CLKSEL0_EXTE \
- $01 constant CLKSEL0_CLKS \
-&81 constant DWDR \ debugWire communication register
-\ EXTERNAL_INTERRUPT
-&105 constant EICRA \ External Interrupt Control Register A
- $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
- $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
- $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
- $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
-&106 constant EICRB \ External Interrupt Control Register B
- $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
- $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
- $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
- $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
-&61 constant EIMSK \ External Interrupt Mask Register
- $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
-&60 constant EIFR \ External Interrupt Flag Register
- $FF constant EIFR_INTF \ External Interrupt Flags
-&107 constant PCMSK0 \ Pin Change Mask Register 0
- $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
-&108 constant PCMSK1 \ Pin Change Mask Register 1
- $1F constant PCMSK1_PCINT \
-&59 constant PCIFR \ Pin Change Interrupt Flag Register
- $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
-&104 constant PCICR \ Pin Change Interrupt Control Register
- $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
-\ USART1
-&206 constant UDR1 \ USART I/O Data Register
-&200 constant UCSR1A \ USART Control and Status Register A
- $80 constant UCSR1A_RXC1 \ USART Receive Complete
- $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
- $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
- $10 constant UCSR1A_FE1 \ Framing Error
- $08 constant UCSR1A_DOR1 \ Data overRun
- $04 constant UCSR1A_UPE1 \ Parity Error
- $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
- $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
-&201 constant UCSR1B \ USART Control and Status Register B
- $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
- $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
- $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
- $10 constant UCSR1B_RXEN1 \ Receiver Enable
- $08 constant UCSR1B_TXEN1 \ Transmitter Enable
- $04 constant UCSR1B_UCSZ12 \ Character Size
- $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
- $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
-&202 constant UCSR1C \ USART Control and Status Register C
- $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
- $30 constant UCSR1C_UPM1 \ Parity Mode Bits
- $08 constant UCSR1C_USBS1 \ Stop Bit Select
- $06 constant UCSR1C_UCSZ1 \ Character Size
- $01 constant UCSR1C_UCPOL1 \ Clock Polarity
-&203 constant UCSR1D \ USART Control and Status Register D
- $02 constant UCSR1D_CTSEN \ CTS Enable
- $01 constant UCSR1D_RTSEN \ RTS Enable
-&204 constant UBRR1 \ USART Baud Rate Register Bytes
-\ WATCHDOG
-&96 constant WDTCSR \ Watchdog Timer Control Register
- $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
- $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
- $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
- $10 constant WDTCSR_WDCE \ Watchdog Change Enable
- $08 constant WDTCSR_WDE \ Watch Dog Enable
-&98 constant WDTCKD \ Watchdog Timer Clock Divider
- $08 constant WDTCKD_WDEWIF \ Watchdog Early Warning Interrupt Flag
- $04 constant WDTCKD_WDEWIE \ Watchdog Early Warning Interrupt Enable
- $03 constant WDTCKD_WCLKD \ Watchdog Timer Clock Dividers
-\ ANALOG_COMPARATOR
-&80 constant ACSR \ Analog Comparator Control And Status Register
- $80 constant ACSR_ACD \ Analog Comparator Disable
- $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
- $20 constant ACSR_ACO \ Analog Compare Output
- $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
- $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
- $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
- $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
-&127 constant DIDR1 \
- $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
- $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
-\ PORTC
-&40 constant PORTC \ Port C Data Register
- $F0 constant PORTC_PORTC \ Port C Data Register bits
- $07 constant PORTC_PORTC \ Port C Data Register bits
-&39 constant DDRC \ Port C Data Direction Register
- $F0 constant DDRC_DDC \ Port C Data Direction Register bits
- $07 constant DDRC_DDC \ Port C Data Direction Register bits
-&38 constant PINC \ Port C Input Pins
- $F0 constant PINC_PINC \ Port C Input Pins bits
- $07 constant PINC_PINC \ Port C Input Pins bits
-
-\ Interrupts
-&2 constant INT0Addr \ External Interrupt Request 0
-&4 constant INT1Addr \ External Interrupt Request 1
-&6 constant INT2Addr \ External Interrupt Request 2
-&8 constant INT3Addr \ External Interrupt Request 3
-&10 constant INT4Addr \ External Interrupt Request 4
-&12 constant INT5Addr \ External Interrupt Request 5
-&14 constant INT6Addr \ External Interrupt Request 6
-&16 constant INT7Addr \ External Interrupt Request 7
-&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
-&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
-&22 constant USB_GENAddr \ USB General Interrupt Request
-&24 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
-&26 constant WDTAddr \ Watchdog Time-out Interrupt
-&28 constant TIMER1_CAPTAddr \ Timer/Counter2 Capture Event
-&30 constant TIMER1_COMPAAddr \ Timer/Counter2 Compare Match B
-&32 constant TIMER1_COMPBAddr \ Timer/Counter2 Compare Match B
-&34 constant TIMER1_COMPCAddr \ Timer/Counter2 Compare Match C
-&36 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-&38 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
-&40 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
-&42 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-&44 constant SPI__STCAddr \ SPI Serial Transfer Complete
-&46 constant USART1__RXAddr \ USART1, Rx Complete
-&48 constant USART1__UDREAddr \ USART1 Data register Empty
-&50 constant USART1__TXAddr \ USART1, Tx Complete
-&52 constant ANALOG_COMPAddr \ Analog Comparator
-&54 constant EE_READYAddr \ EEPROM Ready
-&56 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega8u2/device.asm b/amforth-6.5/avr8/devices/atmega8u2/device.asm
deleted file mode 100644
index e8040e5..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/device.asm
+++ /dev/null
@@ -1,112 +0,0 @@
-; Partname: ATmega8U2
-; generated automatically, do not edit
-
-.nolist
- .include "m8U2def.inc"
-.list
-
-.equ ramstart = 256
-.equ CELLSIZE = 2
-.macro readflashcell
- lsl zl
- rol zh
- lpm @0, Z+
- lpm @1, Z+
-.endmacro
-.macro writeflashcell
- lsl zl
- rol zh
-.endmacro
-.set WANT_PORTB = 0
-.set WANT_PORTD = 0
-.set WANT_SPI = 0
-.set WANT_BOOT_LOAD = 0
-.set WANT_EEPROM = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_PLL = 0
-.set WANT_USB_DEVICE = 0
-.set WANT_CPU = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_USART1 = 0
-.set WANT_WATCHDOG = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_PORTC = 0
-.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.org 2
- rcall isr ; External Interrupt Request 0
-.org 4
- rcall isr ; External Interrupt Request 1
-.org 6
- rcall isr ; External Interrupt Request 2
-.org 8
- rcall isr ; External Interrupt Request 3
-.org 10
- rcall isr ; External Interrupt Request 4
-.org 12
- rcall isr ; External Interrupt Request 5
-.org 14
- rcall isr ; External Interrupt Request 6
-.org 16
- rcall isr ; External Interrupt Request 7
-.org 18
- rcall isr ; Pin Change Interrupt Request 0
-.org 20
- rcall isr ; Pin Change Interrupt Request 1
-.org 22
- rcall isr ; USB General Interrupt Request
-.org 24
- rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
-.org 26
- rcall isr ; Watchdog Time-out Interrupt
-.org 28
- rcall isr ; Timer/Counter2 Capture Event
-.org 30
- rcall isr ; Timer/Counter2 Compare Match B
-.org 32
- rcall isr ; Timer/Counter2 Compare Match B
-.org 34
- rcall isr ; Timer/Counter2 Compare Match C
-.org 36
- rcall isr ; Timer/Counter1 Overflow
-.org 38
- rcall isr ; Timer/Counter0 Compare Match A
-.org 40
- rcall isr ; Timer/Counter0 Compare Match B
-.org 42
- rcall isr ; Timer/Counter0 Overflow
-.org 44
- rcall isr ; SPI Serial Transfer Complete
-.org 46
- rcall isr ; USART1, Rx Complete
-.org 48
- rcall isr ; USART1 Data register Empty
-.org 50
- rcall isr ; USART1, Tx Complete
-.org 52
- rcall isr ; Analog Comparator
-.org 54
- rcall isr ; EEPROM Ready
-.org 56
- rcall isr ; Store Program Memory Read
-.equ INTVECTORS = 29
-.nooverlap
-
-; compatability layer (maybe empty)
-
-; controller data area, environment query mcu-info
-mcu_info:
-mcu_ramsize:
- .dw 512
-mcu_eepromsize:
- .dw 512
-mcu_maxdp:
- .dw 4096
-mcu_numints:
- .dw 29
-mcu_name:
- .dw 9
- .db "ATmega8U2",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8u2/device.inc b/amforth-6.5/avr8/devices/atmega8u2/device.inc
deleted file mode 100644
index bee0007..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/device.inc
+++ /dev/null
@@ -1,1128 +0,0 @@
-; Partname: ATmega8U2
-; generated automatically, no not edit
-
-.if WANT_PORTB == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw 37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw 36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw 35
-
-.endif
-.if WANT_PORTD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw 43
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw 42
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw 41
-
-.endif
-.if WANT_SPI == 1
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw 76
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw 77
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw 78
-
-.endif
-.if WANT_BOOT_LOAD == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Store Program Memory Control Register
-VE_SPMCSR:
- .dw $ff06
- .db "SPMCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPMCSR
-XT_SPMCSR:
- .dw PFA_DOVARIABLE
-PFA_SPMCSR:
- .dw 87
-
-.endif
-.if WANT_EEPROM == 1
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Address Register Low Bytes
-VE_EEAR:
- .dw $ff04
- .db "EEAR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEAR
-XT_EEAR:
- .dw PFA_DOVARIABLE
-PFA_EEAR:
- .dw 65
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw 64
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw 63
-
-.endif
-.if WANT_TIMER_COUNTER_0 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0B:
- .dw $ff05
- .db "OCR0B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0B
-XT_OCR0B:
- .dw PFA_DOVARIABLE
-PFA_OCR0B:
- .dw 72
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Output Compare Register
-VE_OCR0A:
- .dw $ff05
- .db "OCR0A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0A
-XT_OCR0A:
- .dw PFA_DOVARIABLE
-PFA_OCR0A:
- .dw 71
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw 70
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register B
-VE_TCCR0B:
- .dw $ff06
- .db "TCCR0B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0B
-XT_TCCR0B:
- .dw PFA_DOVARIABLE
-PFA_TCCR0B:
- .dw 69
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register A
-VE_TCCR0A:
- .dw $ff06
- .db "TCCR0A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0A
-XT_TCCR0A:
- .dw PFA_DOVARIABLE
-PFA_TCCR0A:
- .dw 68
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Mask Register
-VE_TIMSK0:
- .dw $ff06
- .db "TIMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK0
-XT_TIMSK0:
- .dw PFA_DOVARIABLE
-PFA_TIMSK0:
- .dw 110
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter0 Interrupt Flag register
-VE_TIFR0:
- .dw $ff05
- .db "TIFR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR0
-XT_TIFR0:
- .dw PFA_DOVARIABLE
-PFA_TIFR0:
- .dw 53
-; ( -- addr ) System Constant
-; R( -- )
-; General Timer/Counter Control Register
-VE_GTCCR:
- .dw $ff05
- .db "GTCCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_GTCCR
-XT_GTCCR:
- .dw PFA_DOVARIABLE
-PFA_GTCCR:
- .dw 67
-
-.endif
-.if WANT_TIMER_COUNTER_1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw 128
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw 129
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter 1 Control Register C
-VE_TCCR1C:
- .dw $ff06
- .db "TCCR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1C
-XT_TCCR1C:
- .dw PFA_DOVARIABLE
-PFA_TCCR1C:
- .dw 130
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Bytes
-VE_TCNT1:
- .dw $ff05
- .db "TCNT1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1
-XT_TCNT1:
- .dw PFA_DOVARIABLE
-PFA_TCNT1:
- .dw 132
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register A Bytes
-VE_OCR1A:
- .dw $ff05
- .db "OCR1A",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1A
-XT_OCR1A:
- .dw PFA_DOVARIABLE
-PFA_OCR1A:
- .dw 136
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register B Bytes
-VE_OCR1B:
- .dw $ff05
- .db "OCR1B",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1B
-XT_OCR1B:
- .dw PFA_DOVARIABLE
-PFA_OCR1B:
- .dw 138
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register C Bytes
-VE_OCR1C:
- .dw $ff05
- .db "OCR1C",0
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1C
-XT_OCR1C:
- .dw PFA_DOVARIABLE
-PFA_OCR1C:
- .dw 140
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Bytes
-VE_ICR1:
- .dw $ff04
- .db "ICR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1
-XT_ICR1:
- .dw PFA_DOVARIABLE
-PFA_ICR1:
- .dw 134
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Mask Register
-VE_TIMSK1:
- .dw $ff06
- .db "TIMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK1
-XT_TIMSK1:
- .dw PFA_DOVARIABLE
-PFA_TIMSK1:
- .dw 111
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Interrupt Flag register
-VE_TIFR1:
- .dw $ff05
- .db "TIFR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR1
-XT_TIFR1:
- .dw PFA_DOVARIABLE
-PFA_TIFR1:
- .dw 54
-
-.endif
-.if WANT_PLL == 1
-; ( -- addr ) System Constant
-; R( -- )
-; PLL Status and Control register
-VE_PLLCSR:
- .dw $ff06
- .db "PLLCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_PLLCSR
-XT_PLLCSR:
- .dw PFA_DOVARIABLE
-PFA_PLLCSR:
- .dw 73
-
-.endif
-.if WANT_USB_DEVICE == 1
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINT:
- .dw $ff05
- .db "UEINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINT
-XT_UEINT:
- .dw PFA_DOVARIABLE
-PFA_UEINT:
- .dw 244
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEBCLX:
- .dw $ff06
- .db "UEBCLX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEBCLX
-XT_UEBCLX:
- .dw PFA_DOVARIABLE
-PFA_UEBCLX:
- .dw 242
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEDATX:
- .dw $ff06
- .db "UEDATX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEDATX
-XT_UEDATX:
- .dw PFA_DOVARIABLE
-PFA_UEDATX:
- .dw 241
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEIENX:
- .dw $ff06
- .db "UEIENX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEIENX
-XT_UEIENX:
- .dw PFA_DOVARIABLE
-PFA_UEIENX:
- .dw 240
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA1X:
- .dw $ff07
- .db "UESTA1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA1X
-XT_UESTA1X:
- .dw PFA_DOVARIABLE
-PFA_UESTA1X:
- .dw 239
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UESTA0X:
- .dw $ff07
- .db "UESTA0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UESTA0X
-XT_UESTA0X:
- .dw PFA_DOVARIABLE
-PFA_UESTA0X:
- .dw 238
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG1X:
- .dw $ff07
- .db "UECFG1X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG1X
-XT_UECFG1X:
- .dw PFA_DOVARIABLE
-PFA_UECFG1X:
- .dw 237
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECFG0X:
- .dw $ff07
- .db "UECFG0X",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UECFG0X
-XT_UECFG0X:
- .dw PFA_DOVARIABLE
-PFA_UECFG0X:
- .dw 236
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UECONX:
- .dw $ff06
- .db "UECONX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UECONX
-XT_UECONX:
- .dw PFA_DOVARIABLE
-PFA_UECONX:
- .dw 235
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UERST:
- .dw $ff05
- .db "UERST",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UERST
-XT_UERST:
- .dw PFA_DOVARIABLE
-PFA_UERST:
- .dw 234
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UENUM:
- .dw $ff05
- .db "UENUM",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UENUM
-XT_UENUM:
- .dw PFA_DOVARIABLE
-PFA_UENUM:
- .dw 233
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UEINTX:
- .dw $ff06
- .db "UEINTX"
- .dw VE_HEAD
- .set VE_HEAD=VE_UEINTX
-XT_UEINTX:
- .dw PFA_DOVARIABLE
-PFA_UEINTX:
- .dw 232
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDMFN:
- .dw $ff05
- .db "UDMFN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDMFN
-XT_UDMFN:
- .dw PFA_DOVARIABLE
-PFA_UDMFN:
- .dw 230
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDFNUM:
- .dw $ff06
- .db "UDFNUM"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDFNUM
-XT_UDFNUM:
- .dw PFA_DOVARIABLE
-PFA_UDFNUM:
- .dw 228
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDADDR:
- .dw $ff06
- .db "UDADDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDADDR
-XT_UDADDR:
- .dw PFA_DOVARIABLE
-PFA_UDADDR:
- .dw 227
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDIEN:
- .dw $ff05
- .db "UDIEN",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDIEN
-XT_UDIEN:
- .dw PFA_DOVARIABLE
-PFA_UDIEN:
- .dw 226
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDINT:
- .dw $ff05
- .db "UDINT",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDINT
-XT_UDINT:
- .dw PFA_DOVARIABLE
-PFA_UDINT:
- .dw 225
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_UDCON:
- .dw $ff05
- .db "UDCON",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDCON
-XT_UDCON:
- .dw PFA_DOVARIABLE
-PFA_UDCON:
- .dw 224
-; ( -- addr ) System Constant
-; R( -- )
-; USB General Control Register
-VE_USBCON:
- .dw $ff06
- .db "USBCON"
- .dw VE_HEAD
- .set VE_HEAD=VE_USBCON
-XT_USBCON:
- .dw PFA_DOVARIABLE
-PFA_USBCON:
- .dw 216
-; ( -- addr ) System Constant
-; R( -- )
-; Regulator Control Register
-VE_REGCR:
- .dw $ff05
- .db "REGCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_REGCR
-XT_REGCR:
- .dw PFA_DOVARIABLE
-PFA_REGCR:
- .dw 99
-
-.endif
-.if WANT_CPU == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw 95
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer
-VE_SP:
- .dw $ff02
- .db "SP"
- .dw VE_HEAD
- .set VE_HEAD=VE_SP
-XT_SP:
- .dw PFA_DOVARIABLE
-PFA_SP:
- .dw 93
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw 85
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw 84
-; ( -- addr ) System Constant
-; R( -- )
-; Oscillator Calibration Value
-VE_OSCCAL:
- .dw $ff06
- .db "OSCCAL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OSCCAL
-XT_OSCCAL:
- .dw PFA_DOVARIABLE
-PFA_OSCCAL:
- .dw 102
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKPR:
- .dw $ff05
- .db "CLKPR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKPR
-XT_CLKPR:
- .dw PFA_DOVARIABLE
-PFA_CLKPR:
- .dw 97
-; ( -- addr ) System Constant
-; R( -- )
-; Sleep Mode Control Register
-VE_SMCR:
- .dw $ff04
- .db "SMCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SMCR
-XT_SMCR:
- .dw PFA_DOVARIABLE
-PFA_SMCR:
- .dw 83
-; ( -- addr ) System Constant
-; R( -- )
-; Extended Indirect Register
-VE_EIND:
- .dw $ff04
- .db "EIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIND
-XT_EIND:
- .dw PFA_DOVARIABLE
-PFA_EIND:
- .dw 92
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 2
-VE_GPIOR2:
- .dw $ff06
- .db "GPIOR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR2
-XT_GPIOR2:
- .dw PFA_DOVARIABLE
-PFA_GPIOR2:
- .dw 75
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 1
-VE_GPIOR1:
- .dw $ff06
- .db "GPIOR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR1
-XT_GPIOR1:
- .dw PFA_DOVARIABLE
-PFA_GPIOR1:
- .dw 74
-; ( -- addr ) System Constant
-; R( -- )
-; General Purpose IO Register 0
-VE_GPIOR0:
- .dw $ff06
- .db "GPIOR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_GPIOR0
-XT_GPIOR0:
- .dw PFA_DOVARIABLE
-PFA_GPIOR0:
- .dw 62
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register1
-VE_PRR1:
- .dw $ff04
- .db "PRR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR1
-XT_PRR1:
- .dw PFA_DOVARIABLE
-PFA_PRR1:
- .dw 101
-; ( -- addr ) System Constant
-; R( -- )
-; Power Reduction Register0
-VE_PRR0:
- .dw $ff04
- .db "PRR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PRR0
-XT_PRR0:
- .dw PFA_DOVARIABLE
-PFA_PRR0:
- .dw 100
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSTA:
- .dw $ff06
- .db "CLKSTA"
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSTA
-XT_CLKSTA:
- .dw PFA_DOVARIABLE
-PFA_CLKSTA:
- .dw 210
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL1:
- .dw $ff07
- .db "CLKSEL1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL1
-XT_CLKSEL1:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL1:
- .dw 209
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_CLKSEL0:
- .dw $ff07
- .db "CLKSEL0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_CLKSEL0
-XT_CLKSEL0:
- .dw PFA_DOVARIABLE
-PFA_CLKSEL0:
- .dw 208
-; ( -- addr ) System Constant
-; R( -- )
-; debugWire communication register
-VE_DWDR:
- .dw $ff04
- .db "DWDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_DWDR
-XT_DWDR:
- .dw PFA_DOVARIABLE
-PFA_DWDR:
- .dw 81
-
-.endif
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register A
-VE_EICRA:
- .dw $ff05
- .db "EICRA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRA
-XT_EICRA:
- .dw PFA_DOVARIABLE
-PFA_EICRA:
- .dw 105
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICRB:
- .dw $ff05
- .db "EICRB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EICRB
-XT_EICRB:
- .dw PFA_DOVARIABLE
-PFA_EICRB:
- .dw 106
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw 61
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw 60
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 0
-VE_PCMSK0:
- .dw $ff06
- .db "PCMSK0"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK0
-XT_PCMSK0:
- .dw PFA_DOVARIABLE
-PFA_PCMSK0:
- .dw 107
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Mask Register 1
-VE_PCMSK1:
- .dw $ff06
- .db "PCMSK1"
- .dw VE_HEAD
- .set VE_HEAD=VE_PCMSK1
-XT_PCMSK1:
- .dw PFA_DOVARIABLE
-PFA_PCMSK1:
- .dw 108
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Flag Register
-VE_PCIFR:
- .dw $ff05
- .db "PCIFR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCIFR
-XT_PCIFR:
- .dw PFA_DOVARIABLE
-PFA_PCIFR:
- .dw 59
-; ( -- addr ) System Constant
-; R( -- )
-; Pin Change Interrupt Control Register
-VE_PCICR:
- .dw $ff05
- .db "PCICR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PCICR
-XT_PCICR:
- .dw PFA_DOVARIABLE
-PFA_PCICR:
- .dw 104
-
-.endif
-.if WANT_USART1 == 1
-; ( -- addr ) System Constant
-; R( -- )
-; USART I/O Data Register
-VE_UDR1:
- .dw $ff04
- .db "UDR1"
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR1
-XT_UDR1:
- .dw PFA_DOVARIABLE
-PFA_UDR1:
- .dw 206
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register A
-VE_UCSR1A:
- .dw $ff06
- .db "UCSR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1A
-XT_UCSR1A:
- .dw PFA_DOVARIABLE
-PFA_UCSR1A:
- .dw 200
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register B
-VE_UCSR1B:
- .dw $ff06
- .db "UCSR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1B
-XT_UCSR1B:
- .dw PFA_DOVARIABLE
-PFA_UCSR1B:
- .dw 201
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register C
-VE_UCSR1C:
- .dw $ff06
- .db "UCSR1C"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1C
-XT_UCSR1C:
- .dw PFA_DOVARIABLE
-PFA_UCSR1C:
- .dw 202
-; ( -- addr ) System Constant
-; R( -- )
-; USART Control and Status Register D
-VE_UCSR1D:
- .dw $ff06
- .db "UCSR1D"
- .dw VE_HEAD
- .set VE_HEAD=VE_UCSR1D
-XT_UCSR1D:
- .dw PFA_DOVARIABLE
-PFA_UCSR1D:
- .dw 203
-; ( -- addr ) System Constant
-; R( -- )
-; USART Baud Rate Register Bytes
-VE_UBRR1:
- .dw $ff05
- .db "UBRR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR1
-XT_UBRR1:
- .dw PFA_DOVARIABLE
-PFA_UBRR1:
- .dw 204
-
-.endif
-.if WANT_WATCHDOG == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCSR:
- .dw $ff06
- .db "WDTCSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCSR
-XT_WDTCSR:
- .dw PFA_DOVARIABLE
-PFA_WDTCSR:
- .dw 96
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Clock Divider
-VE_WDTCKD:
- .dw $ff06
- .db "WDTCKD"
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCKD
-XT_WDTCKD:
- .dw PFA_DOVARIABLE
-PFA_WDTCKD:
- .dw 98
-
-.endif
-.if WANT_ANALOG_COMPARATOR == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw 80
-; ( -- addr ) System Constant
-; R( -- )
-;
-VE_DIDR1:
- .dw $ff05
- .db "DIDR1",0
- .dw VE_HEAD
- .set VE_HEAD=VE_DIDR1
-XT_DIDR1:
- .dw PFA_DOVARIABLE
-PFA_DIDR1:
- .dw 127
-
-.endif
-.if WANT_PORTC == 1
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw 40
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Direction Register
-VE_DDRC:
- .dw $ff04
- .db "DDRC"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRC
-XT_DDRC:
- .dw PFA_DOVARIABLE
-PFA_DDRC:
- .dw 39
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Input Pins
-VE_PINC:
- .dw $ff04
- .db "PINC"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINC
-XT_PINC:
- .dw PFA_DOVARIABLE
-PFA_PINC:
- .dw 38
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega8u2/device.py b/amforth-6.5/avr8/devices/atmega8u2/device.py
deleted file mode 100644
index 34d5823..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/device.py
+++ /dev/null
@@ -1,341 +0,0 @@
-# Partname: ATmega8U2
-# generated automatically, do not edit
-MCUREGS = {
- 'PORTB': '&37',
- 'DDRB': '&36',
- 'PINB': '&35',
- 'PORTD': '&43',
- 'DDRD': '&42',
- 'PIND': '&41',
- 'SPCR': '&76',
- 'SPCR_SPIE': '$80',
- 'SPCR_SPE': '$40',
- 'SPCR_DORD': '$20',
- 'SPCR_MSTR': '$10',
- 'SPCR_CPOL': '$08',
- 'SPCR_CPHA': '$04',
- 'SPCR_SPR': '$03',
- 'SPSR': '&77',
- 'SPSR_SPIF': '$80',
- 'SPSR_WCOL': '$40',
- 'SPSR_SPI2X': '$01',
- 'SPDR': '&78',
- 'SPMCSR': '&87',
- 'SPMCSR_SPMIE': '$80',
- 'SPMCSR_RWWSB': '$40',
- 'SPMCSR_SIGRD': '$20',
- 'SPMCSR_RWWSRE': '$10',
- 'SPMCSR_BLBSET': '$08',
- 'SPMCSR_PGWRT': '$04',
- 'SPMCSR_PGERS': '$02',
- 'SPMCSR_SPMEN': '$01',
- 'EEAR': '&65',
- 'EEDR': '&64',
- 'EECR': '&63',
- 'EECR_EEPM': '$30',
- 'EECR_EERIE': '$08',
- 'EECR_EEMPE': '$04',
- 'EECR_EEPE': '$02',
- 'EECR_EERE': '$01',
- 'OCR0B': '&72',
- 'OCR0A': '&71',
- 'TCNT0': '&70',
- 'TCCR0B': '&69',
- 'TCCR0B_FOC0A': '$80',
- 'TCCR0B_FOC0B': '$40',
- 'TCCR0B_WGM02': '$08',
- 'TCCR0B_CS0': '$07',
- 'TCCR0A': '&68',
- 'TCCR0A_COM0A': '$C0',
- 'TCCR0A_COM0B': '$30',
- 'TCCR0A_WGM0': '$03',
- 'TIMSK0': '&110',
- 'TIMSK0_OCIE0B': '$04',
- 'TIMSK0_OCIE0A': '$02',
- 'TIMSK0_TOIE0': '$01',
- 'TIFR0': '&53',
- 'TIFR0_OCF0B': '$04',
- 'TIFR0_OCF0A': '$02',
- 'TIFR0_TOV0': '$01',
- 'GTCCR': '&67',
- 'GTCCR_TSM': '$80',
- 'GTCCR_PSRSYNC': '$01',
- 'TCCR1A': '&128',
- 'TCCR1A_COM1A': '$C0',
- 'TCCR1A_COM1B': '$30',
- 'TCCR1A_COM1C': '$0C',
- 'TCCR1A_WGM1': '$03',
- 'TCCR1B': '&129',
- 'TCCR1B_ICNC1': '$80',
- 'TCCR1B_ICES1': '$40',
- 'TCCR1B_WGM1': '$18',
- 'TCCR1B_CS1': '$07',
- 'TCCR1C': '&130',
- 'TCCR1C_FOC1A': '$80',
- 'TCCR1C_FOC1B': '$40',
- 'TCCR1C_FOC1C': '$20',
- 'TCNT1': '&132',
- 'OCR1A': '&136',
- 'OCR1B': '&138',
- 'OCR1C': '&140',
- 'ICR1': '&134',
- 'TIMSK1': '&111',
- 'TIMSK1_ICIE1': '$20',
- 'TIMSK1_OCIE1C': '$08',
- 'TIMSK1_OCIE1B': '$04',
- 'TIMSK1_OCIE1A': '$02',
- 'TIMSK1_TOIE1': '$01',
- 'TIFR1': '&54',
- 'TIFR1_ICF1': '$20',
- 'TIFR1_OCF1C': '$08',
- 'TIFR1_OCF1B': '$04',
- 'TIFR1_OCF1A': '$02',
- 'TIFR1_TOV1': '$01',
- 'PLLCSR': '&73',
- 'PLLCSR_PLLP': '$1C',
- 'PLLCSR_PLLE': '$02',
- 'PLLCSR_PLOCK': '$01',
- 'UEINT': '&244',
- 'UEBCLX': '&242',
- 'UEDATX': '&241',
- 'UEIENX': '&240',
- 'UEIENX_FLERRE': '$80',
- 'UEIENX_NAKINE': '$40',
- 'UEIENX_NAKOUTE': '$10',
- 'UEIENX_RXSTPE': '$08',
- 'UEIENX_RXOUTE': '$04',
- 'UEIENX_STALLEDE': '$02',
- 'UEIENX_TXINE': '$01',
- 'UESTA1X': '&239',
- 'UESTA1X_CTRLDIR': '$04',
- 'UESTA1X_CURRBK': '$03',
- 'UESTA0X': '&238',
- 'UESTA0X_CFGOK': '$80',
- 'UESTA0X_OVERFI': '$40',
- 'UESTA0X_UNDERFI': '$20',
- 'UESTA0X_DTSEQ': '$0C',
- 'UESTA0X_NBUSYBK': '$03',
- 'UECFG1X': '&237',
- 'UECFG1X_EPSIZE': '$70',
- 'UECFG1X_EPBK': '$0C',
- 'UECFG1X_ALLOC': '$02',
- 'UECFG0X': '&236',
- 'UECFG0X_EPTYPE': '$C0',
- 'UECFG0X_EPDIR': '$01',
- 'UECONX': '&235',
- 'UECONX_STALLRQ': '$20',
- 'UECONX_STALLRQC': '$10',
- 'UECONX_RSTDT': '$08',
- 'UECONX_EPEN': '$01',
- 'UERST': '&234',
- 'UERST_EPRST': '$1F',
- 'UENUM': '&233',
- 'UEINTX': '&232',
- 'UEINTX_FIFOCON': '$80',
- 'UEINTX_NAKINI': '$40',
- 'UEINTX_RWAL': '$20',
- 'UEINTX_NAKOUTI': '$10',
- 'UEINTX_RXSTPI': '$08',
- 'UEINTX_RXOUTI': '$04',
- 'UEINTX_STALLEDI': '$02',
- 'UEINTX_TXINI': '$01',
- 'UDMFN': '&230',
- 'UDMFN_FNCERR': '$10',
- 'UDFNUM': '&228',
- 'UDADDR': '&227',
- 'UDADDR_ADDEN': '$80',
- 'UDADDR_UADD': '$7F',
- 'UDIEN': '&226',
- 'UDIEN_UPRSME': '$40',
- 'UDIEN_EORSME': '$20',
- 'UDIEN_WAKEUPE': '$10',
- 'UDIEN_EORSTE': '$08',
- 'UDIEN_SOFE': '$04',
- 'UDIEN_SUSPE': '$01',
- 'UDINT': '&225',
- 'UDINT_UPRSMI': '$40',
- 'UDINT_EORSMI': '$20',
- 'UDINT_WAKEUPI': '$10',
- 'UDINT_EORSTI': '$08',
- 'UDINT_SOFI': '$04',
- 'UDINT_SUSPI': '$01',
- 'UDCON': '&224',
- 'UDCON_RSTCPU': '$04',
- 'UDCON_RMWKUP': '$02',
- 'UDCON_DETACH': '$01',
- 'USBCON': '&216',
- 'USBCON_USBE': '$80',
- 'USBCON_FRZCLK': '$20',
- 'REGCR': '&99',
- 'REGCR_REGDIS': '$01',
- 'SREG': '&95',
- 'SREG_I': '$80',
- 'SREG_T': '$40',
- 'SREG_H': '$20',
- 'SREG_S': '$10',
- 'SREG_V': '$08',
- 'SREG_N': '$04',
- 'SREG_Z': '$02',
- 'SREG_C': '$01',
- 'SP': '&93',
- 'MCUCR': '&85',
- 'MCUCR_PUD': '$10',
- 'MCUCR_IVSEL': '$02',
- 'MCUCR_IVCE': '$01',
- 'MCUSR': '&84',
- 'MCUSR_USBRF': '$20',
- 'MCUSR_WDRF': '$08',
- 'MCUSR_BORF': '$04',
- 'MCUSR_EXTRF': '$02',
- 'MCUSR_PORF': '$01',
- 'OSCCAL': '&102',
- 'CLKPR': '&97',
- 'CLKPR_CLKPCE': '$80',
- 'CLKPR_CLKPS': '$0F',
- 'SMCR': '&83',
- 'SMCR_SM': '$0E',
- 'SMCR_SE': '$01',
- 'EIND': '&92',
- 'GPIOR2': '&75',
- 'GPIOR2_GPIOR': '$FF',
- 'GPIOR1': '&74',
- 'GPIOR1_GPIOR': '$FF',
- 'GPIOR0': '&62',
- 'GPIOR0_GPIOR07': '$80',
- 'GPIOR0_GPIOR06': '$40',
- 'GPIOR0_GPIOR05': '$20',
- 'GPIOR0_GPIOR04': '$10',
- 'GPIOR0_GPIOR03': '$08',
- 'GPIOR0_GPIOR02': '$04',
- 'GPIOR0_GPIOR01': '$02',
- 'GPIOR0_GPIOR00': '$01',
- 'PRR1': '&101',
- 'PRR1_PRUSB': '$80',
- 'PRR1_PRUSART1': '$01',
- 'PRR0': '&100',
- 'PRR0_PRTIM0': '$20',
- 'PRR0_PRTIM1': '$08',
- 'PRR0_PRSPI': '$04',
- 'CLKSTA': '&210',
- 'CLKSTA_RCON': '$02',
- 'CLKSTA_EXTON': '$01',
- 'CLKSEL1': '&209',
- 'CLKSEL1_RCCKSEL': '$F0',
- 'CLKSEL1_EXCKSEL': '$0F',
- 'CLKSEL0': '&208',
- 'CLKSEL0_RCSUT': '$C0',
- 'CLKSEL0_EXSUT': '$30',
- 'CLKSEL0_RCE': '$08',
- 'CLKSEL0_EXTE': '$04',
- 'CLKSEL0_CLKS': '$01',
- 'DWDR': '&81',
- 'EICRA': '&105',
- 'EICRA_ISC3': '$C0',
- 'EICRA_ISC2': '$30',
- 'EICRA_ISC1': '$0C',
- 'EICRA_ISC0': '$03',
- 'EICRB': '&106',
- 'EICRB_ISC7': '$C0',
- 'EICRB_ISC6': '$30',
- 'EICRB_ISC5': '$0C',
- 'EICRB_ISC4': '$03',
- 'EIMSK': '&61',
- 'EIMSK_INT': '$FF',
- 'EIFR': '&60',
- 'EIFR_INTF': '$FF',
- 'PCMSK0': '&107',
- 'PCMSK0_PCINT': '$FF',
- 'PCMSK1': '&108',
- 'PCMSK1_PCINT': '$1F',
- 'PCIFR': '&59',
- 'PCIFR_PCIF': '$03',
- 'PCICR': '&104',
- 'PCICR_PCIE': '$03',
- 'UDR1': '&206',
- 'UCSR1A': '&200',
- 'UCSR1A_RXC1': '$80',
- 'UCSR1A_TXC1': '$40',
- 'UCSR1A_UDRE1': '$20',
- 'UCSR1A_FE1': '$10',
- 'UCSR1A_DOR1': '$08',
- 'UCSR1A_UPE1': '$04',
- 'UCSR1A_U2X1': '$02',
- 'UCSR1A_MPCM1': '$01',
- 'UCSR1B': '&201',
- 'UCSR1B_RXCIE1': '$80',
- 'UCSR1B_TXCIE1': '$40',
- 'UCSR1B_UDRIE1': '$20',
- 'UCSR1B_RXEN1': '$10',
- 'UCSR1B_TXEN1': '$08',
- 'UCSR1B_UCSZ12': '$04',
- 'UCSR1B_RXB81': '$02',
- 'UCSR1B_TXB81': '$01',
- 'UCSR1C': '&202',
- 'UCSR1C_UMSEL1': '$C0',
- 'UCSR1C_UPM1': '$30',
- 'UCSR1C_USBS1': '$08',
- 'UCSR1C_UCSZ1': '$06',
- 'UCSR1C_UCPOL1': '$01',
- 'UCSR1D': '&203',
- 'UCSR1D_CTSEN': '$02',
- 'UCSR1D_RTSEN': '$01',
- 'UBRR1': '&204',
- 'WDTCSR': '&96',
- 'WDTCSR_WDIF': '$80',
- 'WDTCSR_WDIE': '$40',
- 'WDTCSR_WDP': '$27',
- 'WDTCSR_WDCE': '$10',
- 'WDTCSR_WDE': '$08',
- 'WDTCKD': '&98',
- 'WDTCKD_WDEWIF': '$08',
- 'WDTCKD_WDEWIE': '$04',
- 'WDTCKD_WCLKD': '$03',
- 'ACSR': '&80',
- 'ACSR_ACD': '$80',
- 'ACSR_ACBG': '$40',
- 'ACSR_ACO': '$20',
- 'ACSR_ACI': '$10',
- 'ACSR_ACIE': '$08',
- 'ACSR_ACIC': '$04',
- 'ACSR_ACIS': '$03',
- 'DIDR1': '&127',
- 'DIDR1_AIN1D': '$02',
- 'DIDR1_AIN0D': '$01',
- 'PORTC': '&40',
- 'PORTC_PORTC': '$F0',
- 'PORTC_PORTC': '$07',
- 'DDRC': '&39',
- 'DDRC_DDC': '$F0',
- 'DDRC_DDC': '$07',
- 'PINC': '&38',
- 'PINC_PINC': '$F0',
- 'PINC_PINC': '$07',
- 'INT0Addr': '2',
- 'INT1Addr': '4',
- 'INT2Addr': '6',
- 'INT3Addr': '8',
- 'INT4Addr': '10',
- 'INT5Addr': '12',
- 'INT6Addr': '14',
- 'INT7Addr': '16',
- 'PCINT0Addr': '18',
- 'PCINT1Addr': '20',
- 'USB_GENAddr': '22',
- 'USB_COMAddr': '24',
- 'WDTAddr': '26',
- 'TIMER1_CAPTAddr': '28',
- 'TIMER1_COMPAAddr': '30',
- 'TIMER1_COMPBAddr': '32',
- 'TIMER1_COMPCAddr': '34',
- 'TIMER1_OVFAddr': '36',
- 'TIMER0_COMPAAddr': '38',
- 'TIMER0_COMPBAddr': '40',
- 'TIMER0_OVFAddr': '42',
- 'SPI__STCAddr': '44',
- 'USART1__RXAddr': '46',
- 'USART1__UDREAddr': '48',
- 'USART1__TXAddr': '50',
- 'ANALOG_COMPAddr': '52',
- 'EE_READYAddr': '54',
- 'SPM_READYAddr': '56'
-} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8u2/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8u2/words/no-jtag.asm
deleted file mode 100644
index 352a4bb..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/words/no-jtag.asm
+++ /dev/null
@@ -1,14 +0,0 @@
-; ( -- )
-; ( -- )
-; MCU
-; disable jtag at runtime
-VE_NOJTAG:
- .dw $FF05
- .db "-jtag",0
- .dw VE_HEAD
- .set VE_HEAD = VE_NOJTAG
-XT_NOJTAG:
- .dw PFA_NOJTAG
-PFA_NOJTAG:
-
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8u2/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8u2/words/no-wdt.asm
deleted file mode 100644
index ff6ddd1..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/words/no-wdt.asm
+++ /dev/null
@@ -1,34 +0,0 @@
-; ( -- )
-; MCU
-; disable watch dog timer at runtime
-VE_NOWDT:
- .dw $ff04
- .db "-wdt"
- .dw VE_HEAD
- .set VE_HEAD = VE_NOWDT
-XT_NOWDT:
- .dw PFA_NOWDT
-PFA_NOWDT:
-
- in temp1,SREG
- push temp1
- ; Turn always off global interrupt.
- cli
- ; Reset Watchdog Timer
- wdr
- ; Clear WDRF in MCUSR
- in temp1, MCUSR
- andi temp1, (0xff & (0<<WDRF))
- out MCUSR, temp1
- ; Write logical one to WDCE and WDE
- ; Keep old prescaler setting to prevent unintentional time-out
- in_ temp1, WDTCSR
- ori temp1, (1<<WDCE) | (1<<WDE)
- out_ WDTCSR, temp1
- ; Turn off WDT
- ldi temp1, (0<<WDE)
- out_ WDTCSR, temp1
- ; restore status register
- pop temp1
- out SREG,temp1
- jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8u2/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8u2/words/sleep.asm
deleted file mode 100644
index 256249c..0000000
--- a/amforth-6.5/avr8/devices/atmega8u2/words/sleep.asm
+++ /dev/null
@@ -1,19 +0,0 @@
-; ( mode -- )
-; MCU
-; put the controller into the specified sleep mode
-VE_SLEEP:
- .dw $ff05
- .db "sleep", 0
- .dw VE_HEAD
- .set VE_HEAD = VE_SLEEP
-XT_SLEEP:
- .dw PFA_SLEEP
-PFA_SLEEP:
- andi tosl, 7 ; leave only legal mode bits
- lsl tosl ; move to correct location (bits 3-1)
- ori tosl, 1 ; set the SE bit
- out_ SMCR, tosl ; set the sleep config
- sleep ; nighty-night
- out_ SMCR, zerol ; 0 protects against accidental sleeps
- loadtos ; pop argument from stack
- jmp_ DO_NEXT