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authorDimitri Sokolyuk <demon@dim13.org>2017-06-18 14:38:03 +0200
committerDimitri Sokolyuk <demon@dim13.org>2017-06-18 14:38:03 +0200
commitcf01b391440fc9de43597b907acfc22dba1aa15e (patch)
tree5cef95c1fd6556af1f9b67360fdc8f02eaf8e2cd /j1/verilog/stack.v
parentb468c5579f42134da43d1dccf828300f5c8fb4c3 (diff)
Add j1
Diffstat (limited to 'j1/verilog/stack.v')
m---------j10
-rw-r--r--j1/verilog/stack.v22
2 files changed, 22 insertions, 0 deletions
diff --git a/j1 b/j1
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-Subproject 911439641c002a8f7a6e306ce1b1d3fd4b389fd
diff --git a/j1/verilog/stack.v b/j1/verilog/stack.v
new file mode 100644
index 0000000..e5cee8a
--- /dev/null
+++ b/j1/verilog/stack.v
@@ -0,0 +1,22 @@
+`include "common.h"
+
+module stack
+ #(parameter DEPTH=4)
+ (input wire clk,
+ /* verilator lint_off UNUSED */
+ input wire resetq,
+ /* verilator lint_on UNUSED */
+ input wire [DEPTH-1:0] ra,
+ output wire [`WIDTH-1:0] rd,
+ input wire we,
+ input wire [DEPTH-1:0] wa,
+ input wire [`WIDTH-1:0] wd);
+
+ reg [`WIDTH-1:0] store[0:(2**DEPTH)-1];
+
+ always @(posedge clk)
+ if (we)
+ store[wa] <= wd;
+
+ assign rd = store[ra];
+endmodule