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authorDimitri Sokolyuk <ds@doozer.de>2017-05-23 17:06:09 +0200
committerDimitri Sokolyuk <ds@doozer.de>2017-05-23 17:06:09 +0200
commit6f86ce7057dd7cd1b491e8f09501258822d2ea74 (patch)
treeb3bfa11f0f72d0e1ca7c84d948af20b7494dd26b /j1demo/verilog/ck_div.v
Import j1demo
Diffstat (limited to 'j1demo/verilog/ck_div.v')
-rw-r--r--j1demo/verilog/ck_div.v41
1 files changed, 41 insertions, 0 deletions
diff --git a/j1demo/verilog/ck_div.v b/j1demo/verilog/ck_div.v
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+++ b/j1demo/verilog/ck_div.v
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+module ck_div(
+input ck_in,
+output ck_out,
+input sys_rst_i
+//output locked;
+);
+parameter DIV_BY = 1;
+parameter MULT_BY = 1;
+
+wire ck_fb;
+
+//DCM #(
+// .CLKDV_DIVIDE(DIV_BY),
+// .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
+// .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
+// .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
+//) DCM_inst (
+// .CLK0(ck_fb),
+// .CLKDV(ck_out),
+// .CLKFB(ck_fb), // DCM clock feedback
+// .CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
+// .RST(0)
+//);
+
+DCM #(
+ .CLKFX_MULTIPLY(MULT_BY),
+ .CLKFX_DIVIDE(DIV_BY),
+ .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
+ .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
+ .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
+) DCM_inst (
+ .CLK0(ck_fb),
+ .CLKFX(ck_out),
+ .CLKFB(ck_fb), // DCM clock feedback
+ .CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
+ .RST(0)
+);
+
+//BUFG BUFG_inst(.I(ck_int), .O(ck_out));
+
+endmodule