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diff --git a/docs/j1demo/synth/Makefile b/docs/j1demo/synth/Makefile
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+project = j1
+vendor = xilinx
+family = spartan3s
+part = xc3s1000-4ft256
+top_module = top
+
+vfiles = ../verilog/top.v ../verilog/j1.v ../verilog/ck_div.v ../verilog/uart.v
+
+include xilinx.mk