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authorDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
committerDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
commit67d25d837ac55f28a366c0a3b262e439a6e75fc3 (patch)
treedf7715c7724c5935ab87c807f3b8b4ef529315e3 /amforth-6.5/avr8/devices/atmega169/device.py
parente0d6784e89dba33226c0edb815bb974486fa7c48 (diff)
Add AmForth
Diffstat (limited to 'amforth-6.5/avr8/devices/atmega169/device.py')
-rw-r--r--amforth-6.5/avr8/devices/atmega169/device.py137
1 files changed, 137 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/atmega169/device.py b/amforth-6.5/avr8/devices/atmega169/device.py
new file mode 100644
index 0000000..4dc59ba
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169/device.py
@@ -0,0 +1,137 @@
+# Partname: ATmega169
+# Built using part description XML file version 300
+# generated automatically, do not edit
+MCUREGS = {
+ 'ADCH': '$79',
+ 'ADCL': '$78',
+ 'ADCSRA': '$7A',
+ 'ADCSRB': '$7B',
+ 'ADMUX': '$7C',
+ 'DIDR0': '$7E',
+ 'ACSR': '$50',
+ 'DIDR1': '$7F',
+ 'SPMCSR': '$57',
+ 'CLKPR': '$61',
+ 'GPIOR0': '$3E',
+ 'GPIOR1': '$4A',
+ 'GPIOR2': '$4B',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'OSCCAL': '$66',
+ 'PRR': '$64',
+ 'SMCR': '$53',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SREG': '$5F',
+ 'EEARH': '$42',
+ 'EEARL': '$41',
+ 'EECR': '$3F',
+ 'EEDR': '$40',
+ 'EICRA': '$69',
+ 'EIFR': '$3C',
+ 'EIMSK': '$3D',
+ 'PCMSK0': '$6B',
+ 'PCMSK1': '$6C',
+ 'OCDR': '$51',
+ 'LCDCCR': '$E7',
+ 'LCDCRA': '$E4',
+ 'LCDCRB': '$E5',
+ 'LCDDR0': '$EC',
+ 'LCDDR1': '$ED',
+ 'LCDDR10': '$F6',
+ 'LCDDR11': '$F7',
+ 'LCDDR12': '$F8',
+ 'LCDDR13': '$F9',
+ 'LCDDR15': '$FB',
+ 'LCDDR16': '$FC',
+ 'LCDDR17': '$FD',
+ 'LCDDR18': '$FE',
+ 'LCDDR2': '$EE',
+ 'LCDDR3': '$EF',
+ 'LCDDR5': '$F1',
+ 'LCDDR6': '$F2',
+ 'LCDDR7': '$F3',
+ 'LCDDR8': '$F4',
+ 'LCDFRR': '$E6',
+ 'DDRA': '$21',
+ 'PINA': '$20',
+ 'PORTA': '$22',
+ 'DDRB': '$24',
+ 'PINB': '$23',
+ 'PORTB': '$25',
+ 'DDRC': '$27',
+ 'PINC': '$26',
+ 'PORTC': '$28',
+ 'DDRD': '$2A',
+ 'PIND': '$29',
+ 'PORTD': '$2B',
+ 'DDRE': '$2D',
+ 'PINE': '$2C',
+ 'PORTE': '$2E',
+ 'DDRF': '$30',
+ 'PINF': '$2F',
+ 'PORTF': '$31',
+ 'DDRG': '$33',
+ 'PING': '$32',
+ 'PORTG': '$34',
+ 'SPCR': '$4C',
+ 'SPDR': '$4E',
+ 'SPSR': '$4D',
+ 'GTCCR': '$43',
+ 'OCR0A': '$47',
+ 'TCCR0A': '$44',
+ 'TCNT0': '$46',
+ 'TIFR0': '$35',
+ 'TIMSK0': '$6E',
+ 'ICR1H': '$87',
+ 'ICR1L': '$86',
+ 'OCR1AH': '$89',
+ 'OCR1AL': '$88',
+ 'OCR1BH': '$8B',
+ 'OCR1BL': '$8A',
+ 'TCCR1A': '$80',
+ 'TCCR1B': '$81',
+ 'TCCR1C': '$82',
+ 'TCNT1H': '$85',
+ 'TCNT1L': '$84',
+ 'TIFR1': '$36',
+ 'TIMSK1': '$6F',
+ 'ASSR': '$B6',
+ 'OCR2A': '$B3',
+ 'TCCR2A': '$B0',
+ 'TCNT2': '$B2',
+ 'TIFR2': '$37',
+ 'TIMSK2': '$70',
+ 'UBRR0H': '$C5',
+ 'UBRR0L': '$C4',
+ 'UCSR0A': '$C0',
+ 'UCSR0B': '$C1',
+ 'UCSR0C': '$C2',
+ 'UDR0': '$C6',
+ 'USICR': '$B8',
+ 'USIDR': '$BA',
+ 'USISR': '$B9',
+ 'WDTCR': '$60',
+ 'INT0Addr': '$002',
+ 'PCINT0Addr': '$004',
+ 'PCINT1Addr': '$006',
+ 'TIMER2_COMPAddr': '$008',
+ 'TIMER2_OVFAddr': '$00A',
+ 'TIMER1_CAPTAddr': '$00C',
+ 'TIMER1_COMPAAddr': '$00E',
+ 'TIMER1_COMPBAddr': '$010',
+ 'TIMER1_OVFAddr': '$012',
+ 'TIMER0_COMPAddr': '$014',
+ 'TIMER0_OVFAddr': '$016',
+ 'SPI_STCAddr': '$018',
+ 'USART0_RXAddr': '$01A',
+ 'USART0_UDREAddr': '$01C',
+ 'USART0_TXAddr': '$01E',
+ 'USI_STARTAddr': '$020',
+ 'USI_OVERFLOWAddr': '$022',
+ 'ANALOG_COMPAddr': '$024',
+ 'ADCAddr': '$026',
+ 'EE_READYAddr': '$028',
+ 'SPM_READYAddr': '$02A',
+ 'LCDAddr': '$02C'
+} \ No newline at end of file